发明授权
US07981786B2 Method of fabricating non-volatile memory device having charge trapping layer
失效
制造具有电荷捕获层的非易失性存储器件的方法
- 专利标题： Method of fabricating non-volatile memory device having charge trapping layer
- 专利标题（中）： 制造具有电荷捕获层的非易失性存储器件的方法
-
申请号： US11966231申请日： 2007-12-28
-
公开(公告)号： US07981786B2公开(公告)日： 2011-07-19
- 发明人: Moon Sig Joo , Seung Ho Pyi , Ki Seon Park , Heung Jae Cho , Yong Top Kim
- 申请人： Moon Sig Joo , Seung Ho Pyi , Ki Seon Park , Heung Jae Cho , Yong Top Kim
- 申请人地址： KR Icheon-si
- 专利权人： Hynix Semiconductor Inc.
- 当前专利权人： Hynix Semiconductor Inc.
- 当前专利权人地址： KR Icheon-si
- 代理机构： Marshall, Gerstein & Borun LLP
- 优先权： KR10-2007-0065846 20070629
- 主分类号： H01L21/3205
- IPC分类号： H01L21/3205 ; H01L21/4763 ; H01L21/302 ; H01L21/461
摘要：
A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness.
公开/授权文献
信息查询
IPC分类:
