发明授权
US07987439B2 Method and apparatus for analyzing circuit model by reduction and computer program product for analyzing the circuit model
有权
用于分析电路模型的方法和装置以及用于分析电路模型的计算机程序产品
- 专利标题: Method and apparatus for analyzing circuit model by reduction and computer program product for analyzing the circuit model
- 专利标题(中): 用于分析电路模型的方法和装置以及用于分析电路模型的计算机程序产品
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申请号: US12027732申请日: 2008-02-07
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公开(公告)号: US07987439B2公开(公告)日: 2011-07-26
- 发明人: Hong Bo Che , Young Hwan Kim
- 申请人: Hong Bo Che , Young Hwan Kim
- 申请人地址: KR Pohang, Kyungsangbuk-Do
- 专利权人: Postech Academy-Industry Foundation
- 当前专利权人: Postech Academy-Industry Foundation
- 当前专利权人地址: KR Pohang, Kyungsangbuk-Do
- 代理机构: Perman & Green, LLP
- 优先权: KR10-2007-0019929 20070227
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
Provided are a method and apparatus for analyzing a circuit model by reducing, and a computer program product for analyzing the circuit model. The circuit model at least includes independent current source models, resistance models, and capacitance models. Also, the circuit model forms a resistance capacitance (RC) network with independent current sources. The method includes selecting a node to be removed using resistance information and comparing conductance of a capacitor for a given time step and the total conductance of the node. Further, the method includes removing the selected nodes and generating RC elements and independent current sources using adjacent nodes, which maintain the accuracy of node voltages of a circuit reduced in an accuracy order used for entrywise perturbation of the corresponding circuit equation. Moreover, an efficient method of handling the independent current sources while reducing the circuit is provided.
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