Invention Grant
- Patent Title: Manufacturing method for a semi-conductor on insulator substrate comprising a localised Ge enriched step
- Patent Title (中): 一种半导体绝缘体衬底的制造方法,包括局部富锗步骤
-
Application No.: US12340839Application Date: 2008-12-22
-
Publication No.: US07989327B2Publication Date: 2011-08-02
- Inventor: Benjamin Vincent , Laurent Clavelier , Jean-Francois Damlencourt
- Applicant: Benjamin Vincent , Laurent Clavelier , Jean-Francois Damlencourt
- Applicant Address: FR Paris
- Assignee: Commissariat a l'Energie Atomique
- Current Assignee: Commissariat a l'Energie Atomique
- Current Assignee Address: FR Paris
- Agency: Pearne & Gordon LLP
- Priority: FR0760380 20071227
- Main IPC: H01L21/20
- IPC: H01L21/20

Abstract:
A method of manufacturing a semi-conductor on insulator substrate from an SOI substrate, wherein a Si1-xGex layer is formed on a superficial layer of silicon having a buried electrical insulating layer. A silicon oxide layer is formed on the Si1-xGex layer. The resulting stack of silicon, Si1-xGex and silicon oxide layers is etched up to the buried insulating layer leaving an island of the stack, or up to the superficial layer leaving a zone of silicon and an island of the stack. A mask is formed to protect against oxidation on the etched structure, wherein the protective mask only leaves visible the silicon oxide layer of the island. The germanium of the Si1-xGex layer is condensed on the island to obtain an island comprising a layer that is enriched in germanium, or even a layer of germanium, on the insulating layer, with a silicon oxide layer on top of it.
Public/Granted literature
- US20090170295A1 MANUFACTURING METHOD FOR A SEMI-CONDUCTOR ON INSULATOR SUBSTRATE COMPRISING A LOCALISED Ge ENRICHED STEP Public/Granted day:2009-07-02
Information query
IPC分类: