A power-on reset circuit includes a charge-up circuit to charge a first capacitor after power is on, a first NOR circuit connected to an output terminal of the charge-up circuit and receive a power-on reset signal output from an output terminal of the power-on reset circuit, a first inverter connected to the first NOR circuit, a second capacitor connected between an input terminal of the first NOR circuit and an output terminal of the first inverter, a counter configured to count a clock, a clock selector configured to select whether to output or inhibit a clock signal based on an output signal from the counter, and a second inverter connected to the output terminal of the counter to output the power-on reset signal.