发明授权
US07992059B2 System and method for testing a large memory area during processor design verification and validation
失效
在处理器设计验证和验证期间测试大内存区域的系统和方法
- 专利标题: System and method for testing a large memory area during processor design verification and validation
- 专利标题(中): 在处理器设计验证和验证期间测试大内存区域的系统和方法
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申请号: US11853212申请日: 2007-09-11
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公开(公告)号: US07992059B2公开(公告)日: 2011-08-02
- 发明人: Divya Subbarao Anvekar , Shubhodeep Roy Choudhury , Manoj Dusanapudi , Sunil Suresh Hatti , Shakti Kapoor
- 申请人: Divya Subbarao Anvekar , Shubhodeep Roy Choudhury , Manoj Dusanapudi , Sunil Suresh Hatti , Shakti Kapoor
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: VanLeeuwen & VanLeeuwen
- 代理商 Matthew B. Talpis
- 主分类号: G11C29/00
- IPC分类号: G11C29/00 ; G06F11/00
摘要:
A system and method for replicating a memory block throughout a main memory and modifying real addresses within an address translation buffer to reference the replicated memory blocks during test case set re-executions in order to fully test the main memory is presented. A test case generator generates a test case set (multiple test cases) along with an initial address translation buffer that includes real addresses that reference an initial memory block. A test case executor modifies the real addresses after each test case set re-execution in order for a processor to test each replicated memory block included in the main memory.
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