发明授权
US07992059B2 System and method for testing a large memory area during processor design verification and validation 失效
在处理器设计验证和验证期间测试大内存区域的系统和方法

System and method for testing a large memory area during processor design verification and validation
摘要:
A system and method for replicating a memory block throughout a main memory and modifying real addresses within an address translation buffer to reference the replicated memory blocks during test case set re-executions in order to fully test the main memory is presented. A test case generator generates a test case set (multiple test cases) along with an initial address translation buffer that includes real addresses that reference an initial memory block. A test case executor modifies the real addresses after each test case set re-execution in order for a processor to test each replicated memory block included in the main memory.
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