Invention Grant
- Patent Title: Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same
- Patent Title (中): 具有多层厚度的电介质层的嵌入式晶体管器件及其制造方法
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Application No.: US12167231Application Date: 2008-07-02
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Publication No.: US07994559B2Publication Date: 2011-08-09
- Inventor: Jer-Chyi Wang , Tieh-Chiang Wu , Chung-Yuan Lee , Jeng-Ping Lin
- Applicant: Jer-Chyi Wang , Tieh-Chiang Wu , Chung-Yuan Lee , Jeng-Ping Lin
- Applicant Address: TW Kueishan, Tao-Yuan Hsien
- Assignee: Nanya Technology Corp.
- Current Assignee: Nanya Technology Corp.
- Current Assignee Address: TW Kueishan, Tao-Yuan Hsien
- Agent Winston Hsu; Scott Margo
- Priority: TW96141856A 20071106; TW97117451A 20080512
- Main IPC: H01L21/82
- IPC: H01L21/82

Abstract:
A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.
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