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    RECESSED-GATE TRANSISTOR DEVICE HAVING A DIELECTRIC LAYER WITH MULTI THICKNESSES AND METHOD OF MAKING THE SAME
    1.
    发明申请
    RECESSED-GATE TRANSISTOR DEVICE HAVING A DIELECTRIC LAYER WITH MULTI THICKNESSES AND METHOD OF MAKING THE SAME 有权
    具有多个厚度的电介质层的绝缘栅晶体管器件及其制造方法

    公开(公告)号：US20090114968A1

    公开(公告)日：2009-05-07

    申请号：US12167231

    申请日：2008-07-02

    申请人： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

    发明人： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

    IPC分类号： H01L21/265 ,  H01L29/78 ,  H01L27/108

    CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621

    摘要： A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.

    摘要翻译： 凹入栅极晶体管器件包括嵌入在半导体衬底中形成的栅极沟槽中的栅电极，其中栅极沟槽包括垂直侧壁和U形底部。 源区域设置在半导体衬底内的栅极沟槽的一侧。 漏极区域设置在其另一侧。 在栅电极和半导体衬底之间形成非对称栅介质层。 不对称栅极介电层在栅电极和漏极区之间具有第一厚度，并且在栅极和源极区之间具有第二厚度，其中第一厚度比第二厚度厚。

    ELEVATED CHANNEL FLASH DEVICE AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    ELEVATED CHANNEL FLASH DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    高通道闪光器件及其制造方法

    公开(公告)号：US20090090955A1

    公开(公告)日：2009-04-09

    申请号：US12057391

    申请日：2008-03-28

    申请人： Jer-Chyi Wang ,  Ming-Cheng Chang ,  Yi-Feng Chang ,  Wei-Ming Liao ,  Chien-Chang Huang

    发明人： Jer-Chyi Wang ,  Ming-Cheng Chang ,  Yi-Feng Chang ,  Wei-Ming Liao ,  Chien-Chang Huang

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L29/7887 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7851

    摘要： A FLASH device including a substrate having a protrusive portion integrally formed thereon, two floating gates, a control gate and a dielectric layer is provided. The two floating gates are disposed on two sides of the protrusive portion and respectively covering a portion of the protrusive portion. The control gate is disposed on top of the protrusive portion and sandwiched between the two floating gates. The dielectric layer is disposed between each of the two floating gates and the control gate. Because the control gate of the FLASH device is disposed on the protrusive portion, an elevated channel can be formed. Moreover, because of the position of the two floating gates, an effective floating gate (FG) length can be increased without impacting the cell density.

    摘要翻译： 一种闪存装置，其特征在于，具备：一体地形成有突出部的基板，两个浮置栅极，控制栅极和电介质层。 两个浮动门设置在突出部分的两侧并分别覆盖突出部分的一部分。 控制门设置在突出部分的顶部并夹在两个浮动门之间。 介电层设置在两个浮动栅极和控制栅极之间。 因为FLASH装置的控制门设置在突出部分上，所以可以形成升高的通道。 此外，由于两个浮栅的位置，可以增加有效浮栅（FG）长度而不影响单元密度。

    TWO-BIT FLASH MEMORY CELL STRUCTURE AND METHOD OF MAKING THE SAME
    3.
    发明申请
    TWO-BIT FLASH MEMORY CELL STRUCTURE AND METHOD OF MAKING THE SAME 审中-公开
    双位闪存存储器单元结构及其制造方法

    公开(公告)号：US20090020801A1

    公开(公告)日：2009-01-22

    申请号：US11951344

    申请日：2007-12-06

    申请人： Wei-Ming Liao ,  Ming-Cheng Chang ,  Jer-Chyi Wang

    发明人： Wei-Ming Liao ,  Ming-Cheng Chang ,  Jer-Chyi Wang

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/7887 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825

    摘要： A flash memory cell includes a control gate oxide layer on a substrate, a T-shaped control gate on the control gate oxide layer, a floating gate disposed on two recessed sidewalls of the T-shaped control gate, an insulating layer between the control gate and the floating gate, a dielectric layer between the floating gate and the substrate, a spacer on the sidewall of the floating gate, a P+ source/drain region next to the spacer, and an N+ pocket region encompassing the P+ source/drain region and covering the area directly under the floating gate.

    摘要翻译： 闪存单元包括衬底上的控制栅极氧化层，控制栅极氧化层上的T形控制栅极，设置在T形控制栅极的两个凹入侧壁上的浮置栅极，控制栅极之间的绝缘层 浮置栅极和浮置栅极之间的电介质层，浮置栅极的侧壁上的间隔物，隔着间隔物的P +源极/漏极区域和包围P +源极/漏极区域的N +穴状区域，以及 覆盖浮动门下方的区域。

    TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME
    4.
    发明申请
    TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    双位闪存存储器单元及其制造方法

    公开(公告)号：US20080283904A1

    公开(公告)日：2008-11-20

    申请号：US11828334

    申请日：2007-07-25

    申请人： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Chien-Chang Huang

    发明人： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Chien-Chang Huang

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7887 ,  H01L29/40114

    摘要： A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a gate stacked on the gate oxide layer. A charge storage spacer stack is disposed at either side of the gate. The charge storage spacer stack includes a bottom charge storage layer and an upper spacer layer. An insulating layer is disposed between the charge storage spacer stack and the gate. A liner is disposed underneath the bottom charge storage layer. A source/drain region is disposed at one side of the bottom charge storage layer within the substrate.

    摘要翻译： 两位闪存单元包括衬底，设置在衬底上的栅极氧化物层，堆叠在栅极氧化物层上的栅极。 电荷存储间隔堆叠设置在栅极的任一侧。 电荷存储间隔堆叠包括底部电荷存储层和上部间隔层。 绝缘层设置在电荷存储间隔堆叠和栅极之间。 衬底设置在底部电荷存储层下面。 源极/漏极区域设置在衬底内的底部电荷存储层的一侧。

    RECESSED-GATE TRANSISTOR DEVICE HAVING A DIELECTRIC LAYER WITH MULTI THICKNESSES AND METHOD OF MAKING THE SAME
    5.
    发明申请
    RECESSED-GATE TRANSISTOR DEVICE HAVING A DIELECTRIC LAYER WITH MULTI THICKNESSES AND METHOD OF MAKING THE SAME 有权
    具有多个厚度的电介质层的绝缘栅晶体管器件及其制造方法

    公开(公告)号：US20110256697A1

    公开(公告)日：2011-10-20

    申请号：US13171405

    申请日：2011-06-28

    申请人： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

    发明人： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

    IPC分类号： H01L21/265

    CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621

    摘要： A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.

    摘要翻译： 凹入栅极晶体管器件包括嵌入在半导体衬底中形成的栅极沟槽中的栅电极，其中栅极沟槽包括垂直侧壁和U形底部。 源区域设置在半导体衬底内的栅极沟槽的一侧。 漏极区域设置在其另一侧。 在栅电极和半导体衬底之间形成非对称栅介质层。 不对称栅极介电层在栅电极和漏极区之间具有第一厚度，并且在栅极和源极区之间具有第二厚度，其中第一厚度比第二厚度厚。

    Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same
    6.
    发明授权
    Recessed-gate transistor device having a dielectric layer with multi thicknesses and method of making the same 有权
    具有多层厚度的电介质层的嵌入式晶体管器件及其制造方法

    公开(公告)号：US07994559B2

    公开(公告)日：2011-08-09

    申请号：US12167231

    申请日：2008-07-02

    申请人： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

    发明人： Jer-Chyi Wang ,  Tieh-Chiang Wu ,  Chung-Yuan Lee ,  Jeng-Ping Lin

    IPC分类号： H01L21/82

    CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621

    摘要： A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness.

    摘要翻译： 凹入栅极晶体管器件包括嵌入在半导体衬底中形成的栅极沟槽中的栅电极，其中栅极沟槽包括垂直侧壁和U形底部。 源区域设置在半导体衬底内的栅极沟槽的一侧。 漏极区域设置在其另一侧。 在栅电极和半导体衬底之间形成非对称栅介质层。 不对称栅极介电层在栅电极和漏极区之间具有第一厚度，并且在栅极和源极区之间具有第二厚度，其中第一厚度比第二厚度厚。

    RECESS CHANNEL TRANSISTOR
    7.
    发明申请
    RECESS CHANNEL TRANSISTOR 审中-公开
    录音通道晶体管

    公开(公告)号：US20090267126A1

    公开(公告)日：2009-10-29

    申请号：US12141070

    申请日：2008-06-17

    申请人： Jer-Chyi Wang ,  Wei-Ming Liao

    发明人： Jer-Chyi Wang ,  Wei-Ming Liao

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10876 ,  H01L21/823437 ,  H01L21/823487 ,  H01L27/10823

    摘要： A recess channel transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate, which defines an active area; a gate trench in the active area, wherein the gate trench includes a round lower portion; a recessed gate embedded in the gate trench with a spherical gate portion situated in the round lower portion; a gate oxide layer in the round lower portion between the semiconductor substrate and the spherical gate portion; a source region in the active area at one side of the recessed gate; a drain region in the active area at the other side of the recessed gate; and a channel region between the source region and the drain region, wherein the channel region presents a convex curve profile when viewed from a channel widthwise direction.

    摘要翻译： 凹槽通道晶体管包括半导体衬底; 半导体衬底中的沟槽隔离区域，其限定有源区域; 所述有源区中的栅极沟槽，其中所述栅极沟槽包括圆形下部; 嵌入栅极沟槽中的凹入栅极，其具有位于圆形下部中的球形栅极部分; 在半导体衬底和球形栅极部分之间的圆形下部中的栅氧化层; 在所述凹入栅极的一侧的有源区域中的源极区域; 在所述凹入栅极的另一侧的所述有源区域中的漏极区域; 以及源极区域和漏极区域之间的沟道区域，其中当从沟道宽度方向观察时，沟道区域呈现凸曲线轮廓。

    TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME
    10.
    发明申请
    TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    双位闪存存储器单元及其制造方法

    公开(公告)号：US20080265342A1

    公开(公告)日：2008-10-30

    申请号：US11780482

    申请日：2007-07-20

    申请人： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Chien-Chang Huang

    发明人： Ming-Cheng Chang ,  Wei-Ming Liao ,  Jer-Chyi Wang ,  Chien-Chang Huang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7923 ,  H01L29/40117 ,  H01L29/42348

    摘要： A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a T-shaped gate on the gate oxide layer. A first charge storage layer is disposed at one side of and under the T-shaped gate. A second charge storage layer, which is separated from the first charge storage layer by a bottom portion of the T-shaped gate and the gate oxide layer, is disposed at the other side of and under the T-shaped gate. An insulating layer is disposed between the T-shaped gate and the gate oxide layer. A first source/drain region is disposed at one side of the T-shaped gate within the substrate. A second source/drain region is disposed at the other side of the T-shaped gate within the substrate.

    摘要翻译： 两位闪存单元包括衬底，设置在衬底上的栅极氧化物层，栅极氧化物层上的T形栅极。 第一电荷存储层设置在T形门的一侧和下方。 通过T形栅极和栅极氧化物层的底部与第一电荷存储层分离的第二电荷存储层设置在T形栅极的另一侧和下方。 绝缘层设置在T形栅极和栅极氧化物层之间。 第一源极/漏极区域设置在衬底内的T形栅极的一侧。 第二源极/漏极区域设置在衬底内的T形栅极的另一侧。