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发明授权
US07996614B2 Cache intervention on a separate data bus when on-chip bus has separate read and write data busses 有权
当片上总线具有单独的读写数据总线时，在单独数据总线上进行缓存干预

Cache intervention on a separate data bus when on-chip bus has separate read and write data busses
摘要：
Computer implemented method, system and computer usable program code for processing a data request in a data processing system. A read command requesting data is received from a requesting master device. It is determined whether a cache of a processor can provide the requested data. Responsive to a determination that a cache of a processor can provide the requested data, the requested data is routed to the requesting master device on an intervention data bus of the processor separate from a read data bus and a write data bus of the processor.
摘要（中）：

用于在数据处理系统中处理数据请求的计算机实现的方法，系统和计算机可用程序代码。 从请求主设备接收请求数据的读命令。 确定处理器的高速缓存是否能够提供所请求的数据。 响应于确定处理器的高速缓存可以提供所请求的数据，所请求的数据在与处理器的读取数据总线和写入数据总线分离的处理器的干预数据总线上路由到请求主机设备。

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