Cache Intervention on a Separate Data Bus When On-Chip Bus Has Separate Read and Write Data Busses
    1.
    发明申请
    Cache Intervention on a Separate Data Bus When On-Chip Bus Has Separate Read and Write Data Busses 有权
    当片上总线具有独立的读写数据总线时,在单独数据总线上进行缓存干预

    公开(公告)号:US20090177821A1

    公开(公告)日:2009-07-09

    申请号:US11969256

    申请日:2008-01-04

    IPC分类号: G06F13/00

    CPC分类号: G06F12/0831 G06F2212/1016

    摘要: Computer implemented method, system and computer usable program code for processing a data request in a data processing system. A read command requesting data is received from a requesting master device. It is determined whether a cache of a processor can provide the requested data. Responsive to a determination that a cache of a processor can provide the requested data, the requested data is routed to the requesting master device on an intervention data bus of the processor separate from a read data bus and a write data bus of the processor.

    摘要翻译: 用于在数据处理系统中处理数据请求的计算机实现的方法,系统和计算机可用程序代码。 从请求主设备接收请求数据的读命令。 确定处理器的高速缓存是否能够提供所请求的数据。 响应于确定处理器的高速缓存可以提供所请求的数据,所请求的数据在与处理器的读取数据总线和写入数据总线分离的处理器的干预数据总线上路由到请求主机设备。

    Initializing components of an integrated circuit
    2.
    发明授权
    Initializing components of an integrated circuit 有权
    初始化集成电路的组件

    公开(公告)号:US09075585B2

    公开(公告)日:2015-07-07

    申请号:US13236340

    申请日:2011-09-19

    IPC分类号: G01K7/01 G06F13/00 G06F1/20

    CPC分类号: H03L7/08 G06F1/206

    摘要: Methods, systems, and computer program products for initializing one or more components of a system, the system comprising an integrated circuit that comprises at least one processor, are disclosed. A method includes initializing at least one component of the system, determining a temperature of the integrated circuit using a temperature sensing device embedded on the integrated circuit, comparing the determined temperature to a predetermined suitable temperature operating range of at least one additional component to yield a comparison result, and initializing the at least one additional component based on the comparison result. The at least one additional component may be initialized on the condition that the determined temperature of the integrated circuit is within the predetermined suitable temperature operating range of the at least one additional component.

    摘要翻译: 公开了用于初始化系统的一个或多个组件的方法,系统和计算机程序产品,该系统包括包括至少一个处理器的集成电路。 一种方法包括初始化系统的至少一个部件,使用嵌入集成电路中的温度感测装置来确定集成电路的温度,将所确定的温度与至少一个附加部件的预定合适的温度操作范围进行比较,以产生 比较结果,以及基于比较结果初始化至少一个附加组件。 可以在所确定的集成电路的温度在至少一个附加部件的预定合适的温度操作范围内的条件下,初始化至少一个附加部件。

    Performing SIMD shift and arithmetic operation in non-SIMD architecture
by operation on packed data of sub-operands and carry over-correction
    3.
    发明授权
    Performing SIMD shift and arithmetic operation in non-SIMD architecture by operation on packed data of sub-operands and carry over-correction 失效
    通过对子操作数的打包数据进行操作并进行过度校正,在非SIMD架构中执行SIMD移位和算术运算

    公开(公告)号:US6006316A

    公开(公告)日:1999-12-21

    申请号:US770349

    申请日:1996-12-20

    IPC分类号: G06F7/57 G06F9/302 G06F9/315

    摘要: A microprocessor circuit is disclosed for instructions on an arithmetic/shift function performing standard operations (e.g., ALU instructions or Shift instructions) on instructions in a first cycle of operation, and a correction circuit responsive to the arithmetic/shift function for modifying the standard results provided by the arithmetic/shift function to results required by a SIMD instruction being executed. The arithmetic/shift function is an instruction provided by either an Arithmetic Logic Unit (ALU) or by a shift instruction. The correction circuit passes data, unchanged for logical instructions but provides condition codes according to the SIMD instruction.

    摘要翻译: 公开了一种用于关于在第一操作周期中的指令执行标准操作(例如,ALU指令或移位指令)的算术/移位功能的指令的微处理器电路,以及响应于用于修改标准结果的算术/移位功能的校正电路 由算术/移位函数提供给被执行的SIMD指令所要求的结果。 算术/移位功能是由算术逻辑单元(ALU)或移位指令提供的指令。 校正电路对逻辑指令通过不变的数据,但根据SIMD指令提供条件码。

    Initializing Components of an Integrated Circuit
    4.
    发明申请
    Initializing Components of an Integrated Circuit 有权
    初始化集成电路的组件

    公开(公告)号:US20120032716A1

    公开(公告)日:2012-02-09

    申请号:US13236340

    申请日:2011-09-19

    IPC分类号: H03L7/00

    CPC分类号: H03L7/08 G06F1/206

    摘要: Methods, systems, and computer program products for initializing one or more components of a system, the system comprising an integrated circuit that comprises at least one processor, are disclosed. A method includes initializing at least one component of the system, determining a temperature of the integrated circuit using a temperature sensing device embedded on the integrated circuit, comparing the determined temperature to a predetermined suitable temperature operating range of at least one additional component to yield a comparison result, and initializing the at least one additional component based on the comparison result. The at least one additional component may be initialized on the condition that the determined temperature of the integrated circuit is within the predetermined suitable temperature operating range of the at least one additional component.

    摘要翻译: 公开了用于初始化系统的一个或多个组件的方法,系统和计算机程序产品,该系统包括包括至少一个处理器的集成电路。 一种方法包括初始化系统的至少一个部件,使用嵌入集成电路中的温度感测装置确定集成电路的温度,将所确定的温度与至少一个附加部件的预定合适的温度操作范围进行比较,以产生 比较结果,以及基于比较结果初始化至少一个附加组件。 可以在所确定的集成电路的温度在至少一个附加部件的预定合适的温度操作范围内的条件下,初始化至少一个附加部件。

    Cache intervention on a separate data bus when on-chip bus has separate read and write data busses
    5.
    发明授权
    Cache intervention on a separate data bus when on-chip bus has separate read and write data busses 有权
    当片上总线具有单独的读写数据总线时,在单独数据总线上进行缓存干预

    公开(公告)号:US07996614B2

    公开(公告)日:2011-08-09

    申请号:US11969256

    申请日:2008-01-04

    IPC分类号: G06F12/00 G06F13/00 G06F13/28

    CPC分类号: G06F12/0831 G06F2212/1016

    摘要: Computer implemented method, system and computer usable program code for processing a data request in a data processing system. A read command requesting data is received from a requesting master device. It is determined whether a cache of a processor can provide the requested data. Responsive to a determination that a cache of a processor can provide the requested data, the requested data is routed to the requesting master device on an intervention data bus of the processor separate from a read data bus and a write data bus of the processor.

    摘要翻译: 用于在数据处理系统中处理数据请求的计算机实现的方法,系统和计算机可用程序代码。 从请求主设备接收请求数据的读命令。 确定处理器的高速缓存是否能够提供所请求的数据。 响应于确定处理器的高速缓存可以提供所请求的数据,所请求的数据在与处理器的读取数据总线和写入数据总线分离的处理器的干预数据总线上路由到请求主机设备。