Invention Grant
- Patent Title: Integrated circuit memory devices having vertically arranged strings of memory cells therein and methods of operating same
- Patent Title (中): 具有垂直排列的存储器单元串的集成电路存储器件及其操作方法
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Application No.: US12492209Application Date: 2009-06-26
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Publication No.: US08004893B2Publication Date: 2011-08-23
- Inventor: Jae-Sung Sim , Jung-Dal Choi
- Applicant: Jae-Sung Sim , Jung-Dal Choi
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Myers Bigel Sibley & Sajovec
- Priority: KR10-2008-0064067 20080702
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors. Similarly, a second string selection plug is configured to electrically connect a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors.
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