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    NAND-TYPE FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME
    1.
    发明申请
    NAND-TYPE FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME 审中-公开
    NAND型闪存存储器件及其编程方法

    公开(公告)号：US20150294726A1

    公开(公告)日：2015-10-15

    申请号：US14672372

    申请日：2015-03-30

    申请人： JAE-SUNG SIM ,  JOO-HEON KANG ,  KYUNG-JUN SHIN

    发明人： JAE-SUNG SIM ,  JOO-HEON KANG ,  KYUNG-JUN SHIN

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C16/0483

    摘要： A NAND-type flash memory device and method for programming the NAND-type flash memory device are provided. The method may include applying a voltage of 0 V to an unselected string select line, applying the voltage of 0 V to a selected bit line, applying a supply voltage to a selected string select line, and applying a dummy pass voltage to a dummy word line, the dummy pass voltage being in a range between 0 V to a pass voltage. The method may further include applying the supply voltage to an unselected bit line, applying the pass voltage to a selected word line, applying the pass voltage to an unselected word line; and applying a program voltage to the selected word line.

    摘要翻译： 提供了NAND​​型闪速存储器件和用于对NAND型闪速存储器件进行编程的方法。 该方法可以包括向未选择的串选择线施加0V的电压，将0V的电压施加到所选择的位线，向所选择的串选择线施加电源电压，并将虚拟电压施加到虚拟字 虚拟通过电压在0V至通过电压之间的范围内。 该方法可以进一步包括将电源电压施加到未选择的位线，将通过电压施加到所选择的字线，将通过电压施加到未选择的字线; 以及将程序电压施加到所选择的字线。

    Charge trap memory with avalanche generation inducing layer
    2.
    发明授权
    Charge trap memory with avalanche generation inducing layer 有权
    具有雪崩产生诱导层的电荷陷阱存储器

    公开(公告)号：US07615821B2

    公开(公告)日：2009-11-10

    申请号：US11346659

    申请日：2006-02-03

    申请人： Jae Sung Sim ,  Byung Gook Park ,  Jong Duk Lee ,  Chung Woo Kim

    发明人： Jae Sung Sim ,  Byung Gook Park ,  Jong Duk Lee ,  Chung Woo Kim

    IPC分类号： H01L29/792

    CPC分类号： G11C16/0466 ,  G11C16/0483 ,  H01L29/66833 ,  H01L29/792

    摘要： The present invention discloses a charge trap flash memory cell with multi-doped layers at the active region, a memory array using of the memory cell, and an operating method of the same. The charge trap memory cell structure of the present invention is characterized by forming multi-doped layers at the active region appropriately, and it is a difference from the conventional art. The present invention induces electrons to band-to-band tunnel at the PN junction with the source/drain region by the multi-doped layers, and accelerates the electrons at the reverse bias to generate an avalanche phenomenon. Therefore, the method for operating a memory array of the present invention comprises programming by injecting holes which are generated by the avalanche phenomenon into multi-dielectric layers of each memory cells, and erasing by injecting electrons through an F-N tunneling from channels into the multi-dielectric layers of each memory cells.

    摘要翻译： 本发明公开了一种在有源区域具有多掺杂层的电荷陷阱闪存单元，使用存储单元的存储器阵列及其操作方法。 本发明的电荷陷阱存储单元结构的特征在于在有源区适当地形成多层掺杂层，与现有技术不同。 本发明通过多掺杂层在与源/漏区的PN结处引起电子到带 - 带隧道，并且以反向偏压加速电子以产生雪崩现象。 因此，用于操作本发明的存储器阵列的方法包括通过将由雪崩现象产生的空穴注入到每个存储单元的多个电介质层中来进行编程，以及通过从通道的FN隧道注入电子到多层电介质来擦除， 每个存储单元的电介质层。

    Charge-trap nonvolatile memory devices and methods of fabricating the same
    4.
    发明申请
    Charge-trap nonvolatile memory devices and methods of fabricating the same 有权
    电荷陷阱非易失性存储器件及其制造方法

    公开(公告)号：US20080006872A1

    公开(公告)日：2008-01-10

    申请号：US11700315

    申请日：2007-01-31

    申请人： Chang-Seok Kang ,  Jung-Dal Choi ,  Ju-Hyung Kim ,  Jong-Sun Sel ,  Jae-Sung Sim ,  Sang-Hun Jeon

    发明人： Chang-Seok Kang ,  Jung-Dal Choi ,  Ju-Hyung Kim ,  Jong-Sun Sel ,  Jae-Sung Sim ,  Sang-Hun Jeon

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： Nonvolatile memory devices including device isolation patterns on a semiconductor substrate are provided. The device isolation patterns define a cell active region and a peripheral active region of the semiconductor substrate. Cell gate electrodes are provided that cross over the cell active regions. Memory cell patterns are provided between the cell gate electrodes and the cell active regions and extend toward the device isolation patterns. A tunnel insulation film is provided between the memory cell pattern and the cell active region. Related methods of fabricating nonvolatile memory devices are also provided herein.

    摘要翻译： 提供包括半导体衬底上的器件隔离图案的非易失性存储器件。 器件隔离图案限定半导体衬底的单元有源区和外围有源区。 提供跨越电池有源区的电池栅电极。 在单元栅极电极和单元有源区之间提供存储单元图案，并朝向器件隔离图案延伸。 在存储单元图形和单元有源区之间设置隧道绝缘膜。 本文还提供了制造非易失性存储器件的相关方法。

    Integrated Circuit Memory Devices Having Vertically Arranged Strings of Memory Cells Therein and Methods of Operating Same
    7.
    发明申请
    Integrated Circuit Memory Devices Having Vertically Arranged Strings of Memory Cells Therein and Methods of Operating Same 有权
    具有垂直排列的存储器单元串的集成电路存储器件及其操作方法相同

    公开(公告)号：US20110266607A1

    公开(公告)日：2011-11-03

    申请号：US13181037

    申请日：2011-07-12

    申请人： Jae-Sung Sim ,  Jung-Dal Choi

    发明人： Jae-Sung Sim ,  Jung-Dal Choi

    IPC分类号： H01L27/088

    CPC分类号： H01L27/11551 ,  G11C5/02 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578

    摘要： Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors. Similarly, a second string selection plug is configured to electrically connect a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors.

    摘要翻译： 非易失性存储器件包括第一NAND型EEPROM单元串，其具有在串中串联电连接的第一多个串选择晶体管。 该第一多个串选择晶体管包括第一多个耗尽型晶体管和第一增强型晶体管。 EEPROM单元的第二NAND型串还在其中设置有串联电连接的第二多个串选择晶体管。 第二多个串选择晶体管包括第二多个耗尽型晶体管和第二增强型晶体管。 根据本发明的这些实施例，第一增强型晶体管相对于第二多个耗尽型晶体管中的一个垂直堆叠，并且第二增强型晶体管相对于第一多个耗尽型晶体管之一垂直堆叠 晶体管。 第一串选择插头被配置为将第一增强型晶体管的栅极电连接到第二多个耗尽型晶体管之一的栅电极。 类似地，第二串选择插头被配置为将第二增强型晶体管的栅电极电连接到第一多个耗尽型晶体管之一的栅电极。

    Methods of Forming Charge-Trap Type Non-Volatile Memory Devices
    9.
    发明申请
    Methods of Forming Charge-Trap Type Non-Volatile Memory Devices 有权
    形成电荷陷阱型非易失性存储器件的方法

    公开(公告)号：US20100221886A1

    公开(公告)日：2010-09-02

    申请号：US12766272

    申请日：2010-04-23

    申请人： Jae-Sung Sim ,  Jung-Dal Choi ,  Chang-Seok Kang

    发明人： Jae-Sung Sim ,  Jung-Dal Choi ,  Chang-Seok Kang

    IPC分类号： H01L21/8246

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    摘要： Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate.

    摘要翻译： 形成非易失性存储器件的方法可以包括在半导体衬底上形成隧道绝缘层，并在隧道绝缘层上形成电荷捕获层。 然后可以形成延伸穿过隧道绝缘层和电荷陷阱层并进入半导体衬底的沟槽，使得电荷陷阱层和隧道绝缘层的部分保留在沟槽的相对侧上。 可以在沟槽中形成器件隔离层，并且可以在器件隔离层上和电荷陷阱层的剩余部分上形成阻挡绝缘层。 可以在阻挡绝缘层上形成栅电极，并且可以对阻挡绝缘层和电荷陷阱层的剩余部分进行图案化以在栅电极和半导体衬底之间提供阻挡绝缘图案和电荷陷阱图案。

    Charge-trap type non-volatile memory devices and related methods
    10.
    发明授权
    Charge-trap type non-volatile memory devices and related methods 有权
    充电陷阱型非易失性存储器件及相关方法

    公开(公告)号：US07732856B2

    公开(公告)日：2010-06-08

    申请号：US11724870

    申请日：2007-03-16

    申请人： Jae-Sung Sim ,  Jung-Dal Choi ,  Chang-Seok Kang

    发明人： Jae-Sung Sim ,  Jung-Dal Choi ,  Chang-Seok Kang

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    摘要： Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate. Related structures are also discussed.

    摘要翻译： 形成非易失性存储器件的方法可以包括在半导体衬底上形成隧道绝缘层，并在隧道绝缘层上形成电荷捕获层。 然后可以形成延伸穿过隧道绝缘层和电荷陷阱层并进入半导体衬底的沟槽，使得电荷陷阱层和隧道绝缘层的部分保留在沟槽的相对侧上。 可以在沟槽中形成器件隔离层，并且可以在器件隔离层上和电荷陷阱层的剩余部分上形成阻挡绝缘层。 可以在阻挡绝缘层上形成栅电极，并且可以对阻挡绝缘层和电荷陷阱层的剩余部分进行图案化以在栅电极和半导体衬底之间提供阻挡绝缘图案和电荷陷阱图案。 还讨论了相关结构。