发明授权
US08015359B1 Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit
有权
用于在指令处理电路中利用公共结构进行跟踪验证和维持一致性的方法和系统
- 专利标题： Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit
- 专利标题（中）： 用于在指令处理电路中利用公共结构进行跟踪验证和维持一致性的方法和系统
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申请号： US11782238申请日： 2007-07-24
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公开(公告)号： US08015359B1公开(公告)日： 2011-09-06
- 发明人: John Gregory Favor , Joseph Rowlands , Leonard Eric Shar , Richard Thaik
- 申请人： John Gregory Favor , Joseph Rowlands , Leonard Eric Shar , Richard Thaik
- 申请人地址： US CA Redwood City
- 专利权人： Oracle America, Inc.
- 当前专利权人： Oracle America, Inc.
- 当前专利权人地址： US CA Redwood City
- 代理机构： Osha • Liang LLP
- 主分类号： G06F13/00
- IPC分类号： G06F13/00
摘要：
An instruction processing circuit for a processor is disclosed. The instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution unit of the processor. The instruction processing circuit comprises at least one cache circuit and the processing circuit includes a sequencer and a page translation buffer coupled to the sequencer for trace verification and maintaining coherency between a memory and the at least one cache.
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