发明授权
- 专利标题: Method and system for reducing inter-layer capacitance in integrated circuits
- 专利标题(中): 集成电路中降低层间电容的方法和系统
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申请号: US12156281申请日: 2008-05-30
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公开(公告)号: US08015540B2公开(公告)日: 2011-09-06
- 发明人: Kunal N. Taravade , Neal Callan , Paul G. Filseth
- 申请人: Kunal N. Taravade , Neal Callan , Paul G. Filseth
- 申请人地址: US CA Milpitas
- 专利权人: LSI Corporation
- 当前专利权人: LSI Corporation
- 当前专利权人地址: US CA Milpitas
- 代理机构: Suiter Swantz pc llo
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.
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