发明授权
US08015540B2 Method and system for reducing inter-layer capacitance in integrated circuits 有权
集成电路中降低层间电容的方法和系统

Method and system for reducing inter-layer capacitance in integrated circuits
摘要:
The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.
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