Invention Grant
- Patent Title: Method of forming isolation layer structure and method of manufacturing a semiconductor device including the same
- Patent Title (中): 形成隔离层结构的方法及制造其的半导体器件的制造方法
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Application No.: US12944923Application Date: 2010-11-12
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Publication No.: US08017495B2Publication Date: 2011-09-13
- Inventor: Ju-Wan Kim , Kyu-Tae Na , Min Kim , Seung-Bae Park , Il-Woo Kim , Dae-Young Kwak
- Applicant: Ju-Wan Kim , Kyu-Tae Na , Min Kim , Seung-Bae Park , Il-Woo Kim , Dae-Young Kwak
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG Electronics Co., Ltd.
- Current Assignee: SAMSUNG Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Stanzione & Kim, LLP
- Priority: KR10-2009-0108912 20091112
- Main IPC: H01L21/762
- IPC: H01L21/762

Abstract:
An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in a first region. The first trench has a first width, and the first and third oxide layer patterns have no void therein. The second and fourth oxide layer patterns are sequentially formed in a second trench defined by a second recessed top surface of the substrate and sidewalls of gate structures on the substrate in a second region. The second trench has a second width larger than the first width, and the fourth oxide layer pattern has a void therein.
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