Invention Grant
US08017998B1 Gettering contaminants for integrated circuits formed on a silicon-on-insulator structure
失效
吸收在绝缘体上硅结构上形成的集成电路的污染物
- Patent Title: Gettering contaminants for integrated circuits formed on a silicon-on-insulator structure
- Patent Title (中): 吸收在绝缘体上硅结构上形成的集成电路的污染物
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Application No.: US12555665Application Date: 2009-09-08
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Publication No.: US08017998B1Publication Date: 2011-09-13
- Inventor: Srinivasa R. Banna , Scott Robins
- Applicant: Srinivasa R. Banna , Scott Robins
- Applicant Address: US CA Mountain View
- Assignee: T-RAM Semiconductor, Inc.
- Current Assignee: T-RAM Semiconductor, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: The Webostad Firm
- Main IPC: H01L21/84
- IPC: H01L21/84

Abstract:
Gettering contaminants for formation of integrated circuits on a semiconductor-on-insulator structure is described. A semiconductor-on-insulator structure is configured to attract contaminants. Contaminant attractor regions are formed using ion implantation into a semiconductor layer of the semiconductor-on-insulator structure. The semiconductor layer is located above a buried insulator layer of the semiconductor-on-insulator structure. The contaminant attractor regions are spaced away from active regions. Tiles are located on an upper surface of the buried insulator layer. The contaminant attractor regions are formed adjacent to, in close proximity to, or in the tiles. At least one dielectric layer laterally adjacent to the tiles and is disposed on the upper surface of the buried insulator layer. The at least one dielectric layer at least inhibits lateral migration of contaminants to the active regions.
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