公开(公告)号：US08017998B1

公开(公告)日：2011-09-13

申请号：US12555665

申请日：2009-09-08

Applicant: Srinivasa R. Banna ,  Scott Robins

Inventor： Srinivasa R. Banna ,  Scott Robins

IPC: H01L21/84

CPC classification number: H01L21/84 ,  H01L21/3226 ,  H01L27/1027 ,  H01L27/1203

Abstract: Gettering contaminants for formation of integrated circuits on a semiconductor-on-insulator structure is described. A semiconductor-on-insulator structure is configured to attract contaminants. Contaminant attractor regions are formed using ion implantation into a semiconductor layer of the semiconductor-on-insulator structure. The semiconductor layer is located above a buried insulator layer of the semiconductor-on-insulator structure. The contaminant attractor regions are spaced away from active regions. Tiles are located on an upper surface of the buried insulator layer. The contaminant attractor regions are formed adjacent to, in close proximity to, or in the tiles. At least one dielectric layer laterally adjacent to the tiles and is disposed on the upper surface of the buried insulator layer. The at least one dielectric layer at least inhibits lateral migration of contaminants to the active regions.

Abstract translation: 描述了在绝缘体上半导体结构上形成集成电路的污染物。 绝缘体上半导体结构被配置为吸引污染物。 污染物吸引子区域使用离子注入形成到绝缘体上半导体结构的半导体层中。 半导体层位于绝缘体上半导体结构的掩埋绝缘体层的上方。 污染物吸引子区域与活性区域间隔开。 瓷砖位于掩埋绝缘体层的上表面。 污染物吸引子区域形成在瓷砖附近，靠近或在瓷砖中。 与瓷砖横向相邻的至少一个电介质层并且设置在掩埋绝缘体层的上表面上。 至少一个介电层至少抑制污染物向活性区域的横向迁移。

公开(公告)号：US07968381B1

公开(公告)日：2011-06-28

申请号：US11581316

申请日：2006-10-16

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L21/332

CPC classification number: H01L29/7436 ,  H01L27/1027 ,  H01L29/87

Abstract: A semiconductor device having a thyristor-based device and a pass device exhibits characteristics that may include, for example, resistance to short channel effects that occur when conventional MOSFET devices are scaled smaller in connection with advancing technology. According to an example embodiment of the present invention, the semiconductor device includes a pass device having a channel in a fin portion over a semiconductor substrate, and a thyristor device coupled to the pass device. The fin has a top portion and a side portion and extends over the semiconductor substrate. The pass device includes source/drain regions separated by the channel and a gate facing and capacitively coupled to the side portion of the fin that includes the channel. The thyristor device includes anode and cathode end portions, each end portion having base and emitter regions, where one of the emitter regions is coupled to one of the source/drain regions of the pass device. The gate of the pass device is further adapted to switch the pass device between a blocking state and a conducting state via the capacitive coupling and form a conductive path between the source/drain regions. A control port is capacitively coupled to the base region of the end portion of the thyristor that is coupled to the source/drain region of the pass gate and is adapted to facilitate switching of the thyristor between blocking and conducting states.

Abstract translation: 具有基于晶闸管的器件和通过器件的半导体器件表现出特性，其可以包括例如当传统MOSFET器件与前进技术相比缩小时发生的短沟道效应的阻力。 根据本发明的示例实施例，半导体器件包括通过器件，其具有在半导体衬底上的鳍部分中的沟道，以及耦合到通过器件的晶闸管器件。 翅片具有顶部和侧部并且在半导体衬底上延伸。 通过装置包括由通道分离的源极/漏极区域和面对并电容耦合到包括通道的鳍片的侧部的门。 晶闸管器件包括阳极和阴极端部，每个端部具有基极和发射极区域，其中发射极区域之一耦合到通过器件的源极/漏极区域之一。 通过装置的栅极还适于经由电容耦合在阻塞状态和导通状态之间切换通过装置，并在源/漏区之间形成导电路径。 控制端口电容耦合到晶闸管的端部的基极区域，该基极区域耦合到栅极的源极/漏极区域并且适于促进晶闸管在阻塞和导通状态之间的切换。

公开(公告)号：US07894256B1

公开(公告)日：2011-02-22

申请号：US11881159

申请日：2007-07-25

Applicant: Farid Nemati ,  Scott Robins ,  Kevin J. Yang

Inventor： Farid Nemati ,  Scott Robins ,  Kevin J. Yang

IPC: G11C11/39

CPC classification number: G11C11/39 ,  H01L27/1027 ,  H01L29/66393 ,  H01L29/7436

Abstract: A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. The memory cell contains a thyristor body and a gate. The thyristor body has two end region and two base regions, and it is disposed on top of a well. The memory cell is positioned between two isolation regions, and the isolation regions are extended below the well. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.

Abstract translation: 新的存储单元仅包含一个晶闸管，而不需要包括一个存取晶体管。 可以在体硅晶片上制造包含这些存储单元的存储器阵列。 存储单元包含晶闸管体和栅极。 晶闸管体具有两个端部区域和两个基极区域，并且它设置在阱的顶部。 存储单元位于两个隔离区之间，并且隔离区延伸到阱的下方。 第一端区连接到字线，位线和第三线之一。 第二端区连接到字线，位线和第三线中的另一端。 门连接到字线，位线和第三行的剩余部分。

公开(公告)号：US07894255B1

公开(公告)日：2011-02-22

申请号：US11881049

申请日：2007-07-25

Applicant: Farid Nemati ,  Scott Robins ,  Kevin J. Yang

Inventor： Farid Nemati ,  Scott Robins ,  Kevin J. Yang

IPC: G11C11/34

CPC classification number: G11C11/39 ,  H01L27/1027 ,  H01L29/66393 ,  H01L29/7436

Abstract: A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. Each memory cell is separated from other memory cells by shallow trench isolation regions. The memory cell comprises a thyristor body and a gate. The thyristor body has two end region and two base regions. The gate is positioned over and insulated from at least a portion of one base region and offset from another base region. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.

Abstract translation: 新的存储单元仅包含一个晶闸管，而不需要包括一个存取晶体管。 可以在体硅晶片上制造包含这些存储单元的存储器阵列。 每个存储单元通过浅沟槽隔离区与其它存储单元分离。 存储单元包括可控硅体和栅极。 晶闸管体具有两个端部区域和两个基极区域。 栅极定位在一个基极区域的至少一部分上并与另一个基极区域偏移绝缘。 第一端区连接到字线，位线和第三线之一。 第二端区连接到字线，位线和第三线中的另一端。 门连接到字线，位线和第三行的剩余部分。

公开(公告)号：US20090162979A1

公开(公告)日：2009-06-25

申请号：US12367891

申请日：2009-02-09

Applicant: Kevin J. Yang ,  Farid Nemati ,  Scott Robins ,  James D. Plummer ,  Hyun-Jin Cho

Inventor： Kevin J. Yang ,  Farid Nemati ,  Scott Robins ,  James D. Plummer ,  Hyun-Jin Cho

IPC: H01L21/266

CPC classification number: G11C11/39 ,  H01L29/7436 ,  H01L29/749

Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

Abstract translation: 在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。 可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。 因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。 在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

公开(公告)号：US07320895B1

公开(公告)日：2008-01-22

申请号：US11086113

申请日：2005-03-22

Applicant: Andrew Horch ,  Scott Robins ,  Farid Nemati

Inventor： Andrew Horch ,  Scott Robins ,  Farid Nemati

IPC: H01L21/00 ,  H01L21/332

CPC classification number: G11C11/39 ,  H01L27/1025 ,  H01L27/1027 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L29/7436

Abstract: Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port. In this manner, power consumption for a switching operation can be reduced, which is useful, for example, to correspond with reduced power supplied to other devices in a semiconductor device employing the thyristor.

Abstract translation: 使用适于在阻塞状态和导通状态之间切换的基于晶闸管的半导体器件来增强诸如存储器件中使用的切换操作。 根据本发明的示例性实施例，基于晶闸管的半导体器件包括分别具有耦合在第一和第二发射极区之间的第一和第二基极区域的晶闸管。 第一控制端口将第一信号电容耦合到第一基区，并且第二控制端口将第二信号电容耦合到第二基区。 第一和第二信号中的每一个具有极性相反的电荷，相反的极性信号相对于仅具有一个控制端口的晶闸管所需的功率，以较低的功率影响晶闸管的开关。 以这种方式，可以减少用于开关操作的功耗，这对于例如提供给采用晶闸管的半导体器件中的其它器件的降低的功率是有用的。

公开(公告)号：US07125753B1

公开(公告)日：2006-10-24

申请号：US11159738

申请日：2005-06-23

Applicant: Andrew Horch ,  Scott Robins ,  Farid Nemati

Inventor： Andrew Horch ,  Scott Robins ,  Farid Nemati

IPC: H01L21/332

CPC classification number: H01L29/7436 ,  H01L29/66393

Abstract: A semiconductor memory device having a thyristor is manufactured in a manner that makes possible self-alignment of one or more portions of the thyristor. According to an example embodiment of the present invention, a gate is formed over a first portion of doped substrate. The gate is used to mask a portion of the doped substrate and a second portion of the substrate is doped before or after a spacer is formed. After the second portion of the substrate is doped, the spacer is then formed adjacent to the gate and used to mask the second portion of the substrate while a third portion of the substrate is doped. The gate and spacer are thus used to form self-aligned doped portions of the substrate, wherein the first and second portions form base regions and the third portion form an emitter region of a thyristor. In another implementation, the spacer is also adapted to prevent formation of salicide on the portion of the thyristor beneath the spacer, self-aligning the salicide to the junction between the second and third portions. In addition, dimensions such as width and other characteristics of the doped portions that are used to form a thyristor can be controlled without necessarily using a separate mask.

Abstract translation: 制造具有晶闸管的半导体存储器件以能够使晶闸管的一个或多个部分自对准的方式。 根据本发明的示例性实施例，在掺杂衬底的第一部分上形成栅极。 栅极用于掩模掺杂衬底的一部分，并且衬底的第二部分在形成间隔物之前或之后被掺杂。 在衬底的第二部分被掺杂之后，然后在衬底的第三部分被掺杂的同时，将衬底形成为邻近栅极并用于掩蔽衬底的第二部分。 因此，栅极和间隔物用于形成衬底的自对准掺杂部分，其中第一和第二部分形成基极区域，第三部分形成晶闸管的发射极区域。 在另一实施方案中，间隔物还适于防止在间隔物下方的可控硅部分上形成自对准硅化物，使自对准硅化物与第二和第三部分之间的连接处。 此外，可以控制用于形成晶闸管的掺杂部分的宽度和其它特性的尺寸，而不必使用单独的掩模。

公开(公告)号：US07037763B1

公开(公告)日：2006-05-02

申请号：US10739859

申请日：2003-12-18

Applicant: Farid Nemati ,  Scott Robins ,  Andrew E. Horch

Inventor： Farid Nemati ,  Scott Robins ,  Andrew E. Horch

IPC: H01L21/332

CPC classification number: H01L27/0817 ,  H01L29/742 ,  H01L29/7436

Abstract: In an example gated-thyristor circuit, formation of thyristor body regions involves an angled implant of a thyristor body region, such as a base region, to mitigate capacitive coupling of a gated voltage pulse from the thyristor gate to a body region that is not underlying the thyristor gate. According to a more particular example embodiment, such a thyristor switches between a current-passing mode and a current blocking mode in response to at least one voltage pulse coupling to an underlying thyristor base region. Using a first ion type to provide one polarity, an immediately-adjacent thyristor base region is angle implanted through an emitter body region that is located to other side of the adjacent thyristor base region. The emitter body region is then implanted using ions of another ion type to provide the opposite polarity. This angle implantation permits definition of the adjacent thyristor base region sufficiently distant from (e.g., underlapping) the gate to mitigate gate-induced leakage to the second body region and the associated junction leakage between thyristor base regions. Applications include a variety of circuits benefiting from fast-switching and/or small-architecture features; example applications include thyristor-based latches and memory cells and power thyristor circuits.

Abstract translation: 在示例性的门控晶闸管电路中，晶闸管体区域的形成涉及晶闸管本体区域（例如基极区域）的成角度注入，以缓解门控电压脉冲从晶闸管门极到不是底层的体区域的电容耦合 晶闸管门。 根据更具体的示例性实施例，这种晶闸管响应于至少一个连接到下游晶闸管基极区域的电压脉冲而在电流通过模式和电流阻塞模式之间切换。 使用第一离子型来提供一个极性，通过位于相邻晶闸管基极区域的另一侧的发射体体区域，直接注入相邻的晶闸管基极区域。 然后使用另一离子型离子注入发射体体区域以提供相反的极性。 该角度注入允许定义足够远离（例如，重叠）栅极的相邻晶闸管基极区域，以减轻栅极引起的泄漏到第二体区域以及晶闸管基极区域之间的相关连结泄漏。 应用包括受益于快速切换和/或小型架构特性的各种电路; 示例应用包括基于晶闸管的锁存器和存储器单元和功率晶闸管电路。

公开(公告)号：US07030425B1

公开(公告)日：2006-04-18

申请号：US10262696

申请日：2002-10-01

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L29/74

CPC classification number: H01L27/0817 ,  H01L29/41716 ,  H01L29/742

Abstract: A semiconductor device includes a thyristor having at least one body region thereof disposed in a substrate, and a filled trench having a conductive material. According to an example embodiment of the present invention, a conductive material having a narrow upper portion over a relatively wide lower portion is in a filled trench adjacent to at least one thyristor body region in a substrate. In one implementation, a thyristor control port is located over the wide lower portion and adjacent to the narrow upper portion of the conductive shunt and is adapted for capacitively coupling to the thyristor body region in the substrate for controlling current in the thyristor. In another implementation, the conductive material is electrically coupled to a buried emitter region of the thyristor and arranged for shunting current between the buried emitter region and a circuit node near an upper portion of the conductive material. With these approaches, conductive material can be used to fill a portion of the trench that electrically isolates a portion of a thyristor body in a substrate and/or to shunt current between a circuit node in the substrate, such as a buried emitter region, and an upper circuit node.

Abstract translation: 半导体器件包括其中至少一个体区设置在衬底中的晶闸管和具有导电材料的填充沟槽。 根据本发明的示例性实施例，在相对较宽的下部具有窄上部的导电材料在与衬底中的至少一个可控硅体区相邻的填充沟槽中。 在一个实施方式中，晶闸管控制端口位于宽的下部并且与导电分流器的窄上部相邻并且适于电容耦合到用于控制晶闸管中的电流的基板中的晶闸管主体区域。 在另一实施方案中，导电材料电耦合到晶闸管的掩埋发射极区域，并且被布置用于在掩埋发射极区域和导电材料的上部附近的电路节点之间分流电流。 利用这些方法，可以使用导电材料来填充沟槽的一部分，该沟槽电化隔离衬底中的可控硅体的一部分和/或在衬底中的电路节点（例如埋入发射极区域）之间分流电流，和 上电路节点。

公开(公告)号：US06835997B1

公开(公告)日：2004-12-28

申请号：US10282294

申请日：2002-10-28

Applicant: Andrew Horch ,  Scott Robins

Inventor： Andrew Horch ,  Scott Robins

IPC: H01L2900

CPC classification number: H01L29/66363 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/763 ,  H01L27/0617 ,  H01L27/0817

Abstract: A thyristor-based semiconductor device includes a thyristor body that has at least one region in the substrate and a thyristor control port in a trenched region of the device substrate. According to an example embodiment of the present invention, the trench is at least partially filled with a dielectric material and a control port adapted to capacitively couple to the at least one thyristor body region in the substrate. In a more specific implementation, the dielectric material includes deposited dielectric material that is adapted to exhibit resistance to voltage-induced stress that thermally-grown dielectric materials generally exhibit. In another implementation, the dielectric material includes thermally-grown dielectric material, and when used in connection with highly-doped material in the trench, grows faster on the highly-doped material than on a sidewall of the trench that faces the at least on thyristor body region in the substrate. In still another implementation, the dielectric material includes both a thermally-grown dielectric material and a deposited dielectric material. These approaches are particularly useful, for example, in high-density and other applications where thermally-stable dielectric materials are desirable and/or where dielectric material growth at different rates is desirable.

Abstract translation: 基于晶闸管的半导体器件包括晶体管本体，其在衬底中具有至少一个区域，并且在器件衬底的沟槽区域中具有晶闸管控制端口。 根据本发明的示例实施例，沟槽至少部分地填充有电介质材料和适于电容耦合到衬底中的至少一个可控硅体区域的控制端口。 在更具体的实施方案中，电介质材料包括沉积的电介质材料，其适于显示耐热生长的电介质材料通常表现出的电压诱发应力。 在另一个实施方案中，电介质材料包括热生长的介电材料，并且当与沟槽中的高度掺杂材料结合使用时，在高掺杂材料上比在面向至少可控硅的沟槽的侧壁上生长得更快 基体中的体区。 在另一个实施方式中，电介质材料包括热生长介电材料和沉积的电介质材料。 这些方法特别有用，例如在高密度和其他需要热稳定介电材料的应用中，和/或其中需要不同速率的介电材料生长。