Invention Grant
US08019566B2 System and method for efficiently testing cache congruence classes during processor design verification and validation
有权
在处理器设计验证和验证期间有效测试缓存一致性类的系统和方法
- Patent Title: System and method for efficiently testing cache congruence classes during processor design verification and validation
- Patent Title (中): 在处理器设计验证和验证期间有效测试缓存一致性类的系统和方法
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Application No.: US11853154Application Date: 2007-09-11
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Publication No.: US08019566B2Publication Date: 2011-09-13
- Inventor: Vinod Bussa , Shubhodeep Roy Choudhury , Manoj Dusanapudi , Sunil Suresh Hatti , Shakti Kapoor , Batchu Naga Venkata Satyanarayana
- Applicant: Vinod Bussa , Shubhodeep Roy Choudhury , Manoj Dusanapudi , Sunil Suresh Hatti , Shakti Kapoor , Batchu Naga Venkata Satyanarayana
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Van Leeuwen & Van Leeuwen
- Agent Matthew B. Talpis
- Main IPC: G06F11/26
- IPC: G06F11/26 ; G06F11/00

Abstract:
A system and method for using a single test case to test each sector within multiple congruence classes is presented. A test case generator builds a test case for accessing each sector within a congruence class. Since a congruence class spans multiple congruence pages, the test case generator builds the test case over multiple congruence pages in order for the test case to test the entire congruence class. During design verification and validation, a test case executor modifies a congruence class identifier (e.g., patches a base register), which forces the test case to test a specific congruence class. By incrementing the congruence class identifier after each execution of the test case, the test case executor is able to test each congruence class in the cache using a single test case.
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