发明授权
US08030153B2 High voltage TMOS semiconductor device with low gate charge structure and method of making
有权
具有低栅极电荷结构的高电压TMOS半导体器件和制造方法
- 专利标题： High voltage TMOS semiconductor device with low gate charge structure and method of making
- 专利标题（中）： 具有低栅极电荷结构的高电压TMOS半导体器件和制造方法
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申请号： US11932070申请日： 2007-10-31
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公开(公告)号： US08030153B2公开(公告)日： 2011-10-04
- 发明人: Peilin Wang , Edouard D. de Frésart , Ganming Qin , Hongwei Zhou
- 申请人： Peilin Wang , Edouard D. de Frésart , Ganming Qin , Hongwei Zhou
- 申请人地址： US TX Austin
- 专利权人： Freescale Semiconductor, Inc.
- 当前专利权人： Freescale Semiconductor, Inc.
- 当前专利权人地址： US TX Austin
- 代理商 Michael J. Balconi-Lamica
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238
摘要：
A TMOS device (10) is formed using a semiconductor layer (16) of a first type. First and second regions (62,64) of the second type are formed in the semiconductor layer and are spaced apart. A third region (68) is formed in the semiconductor layer by implanting. The third region is between and contacts the first and second doped regions, is of the second conductivity type, and is less heavily doped than the first and second doped regions. A gate stack (67) is formed over a portion of the first doped region, a portion of the second doped region, and the third doped region. By implanting after forming the gate stack, fourth and fifth regions (98,100) of the first type are formed in interior portions of the first and second doped regions, respectively. The third region being of the same conductivity type as the first and second regions reduces Miller capacitance.
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