High voltage TMOS semiconductor device with low gate charge structure and method of making
    1.
    发明授权
    High voltage TMOS semiconductor device with low gate charge structure and method of making 有权
    具有低栅极电荷结构的高电压TMOS半导体器件和制造方法

    公开(公告)号:US08030153B2

    公开(公告)日:2011-10-04

    申请号:US11932070

    申请日:2007-10-31

    IPC分类号: H01L21/8238

    摘要: A TMOS device (10) is formed using a semiconductor layer (16) of a first type. First and second regions (62,64) of the second type are formed in the semiconductor layer and are spaced apart. A third region (68) is formed in the semiconductor layer by implanting. The third region is between and contacts the first and second doped regions, is of the second conductivity type, and is less heavily doped than the first and second doped regions. A gate stack (67) is formed over a portion of the first doped region, a portion of the second doped region, and the third doped region. By implanting after forming the gate stack, fourth and fifth regions (98,100) of the first type are formed in interior portions of the first and second doped regions, respectively. The third region being of the same conductivity type as the first and second regions reduces Miller capacitance.

    摘要翻译: 使用第一类型的半导体层(16)形成TMOS器件(10)。 第二类型的第一和第二区域(62,64)形成在半导体层中并且间隔开。 通过注入在半导体层中形成第三区域(68)。 第三区域在第一和第二掺杂区域之间并且与第一和第二掺杂区域接触,具有第二导电类型,并且比第一和第二掺杂区域重掺杂。 栅极堆叠(67)形成在第一掺杂区域的一部分,第二掺杂区域的一部分和第三掺杂区域上。 通过在形成栅叠层之后注入,第一类型的第四和第五区(98,100)分别形成在第一和第二掺杂区的内部。 与第一和第二区域具有相同导电类型的第三区域减小了米勒电容。

    Trench FET with Source Recess Etch
    2.
    发明申请
    Trench FET with Source Recess Etch 有权
    沟槽FET,源栅槽蚀刻

    公开(公告)号:US20130344667A1

    公开(公告)日:2013-12-26

    申请号:US13528375

    申请日:2012-06-20

    IPC分类号: H01L21/336

    摘要: A high voltage vertical field effect transistor device (101) is fabricated in a substrate (102, 104) using angled implantations (116, 120) into trench sidewalls formed above recessed gate poly layers (114) to form self-aligned N+ regions (123) adjacent to the trenches and along an upper region of an elevated substrate. With a trench fill insulator layer (124) formed over the recessed gate poly layers (114), self-aligned P+ body contact regions (128) are implanted into the elevated substrate without counter-doping the self-aligned N+ regions (123), and a subsequent recess etch removes the elevated substrate, leaving self-aligned N+ source regions (135-142) and P+ body contact regions (130-134).

    摘要翻译: 使用成角度的注入(116,120)形成在形成自对准N +区域(123)的沟槽侧壁中的衬底(102,104)中来制造高电压垂直场效应晶体管器件(101) )并且沿着升高的基底的上部区域。 利用形成在凹陷多晶硅层(114)上方的沟槽填充绝缘体层(124),将自对准P +体接触区域(128)注入升高的衬底中,而不会反向掺杂自对准的N +区域(123) 并且随后的凹陷蚀刻去除升高的衬底,留下自对准的N +源区(135-142)和P +体接触区(130-134)。

    Trench FET with source recess etch
    3.
    发明授权
    Trench FET with source recess etch 有权
    沟槽FET,源凹槽蚀刻

    公开(公告)号:US08895394B2

    公开(公告)日:2014-11-25

    申请号:US13528375

    申请日:2012-06-20

    摘要: A high voltage vertical field effect transistor device (101) is fabricated in a substrate (102, 104) using angled implantations (116, 120) into trench sidewalls formed above recessed gate poly layers (114) to form self-aligned N+ regions (123) adjacent to the trenches and along an upper region of an elevated substrate. With a trench fill insulator layer (124) formed over the recessed gate poly layers (114), self-aligned P+ body contact regions (128) are implanted into the elevated substrate without counter-doping the self-aligned N+ regions (123), and a subsequent recess etch removes the elevated substrate, leaving self-aligned N+ source regions (135-142) and P+ body contact regions (130-134).

    摘要翻译: 使用成角度的注入(116,120)形成在形成自对准N +区域(123)的沟槽侧壁中的衬底(102,104)中来制造高电压垂直场效应晶体管器件(101) )并且沿着升高的基底的上部区域。 利用形成在凹陷多晶硅层(114)上方的沟槽填充绝缘体层(124),将自对准P +体接触区域(128)注入升高的衬底中,而不会反向掺杂自对准的N +区域(123) 并且随后的凹陷蚀刻去除升高的衬底,留下自对准的N +源区(135-142)和P +体接触区(130-134)。

    HIGH VOLTAGE TMOS SEMICONDUCTOR DEVICE WITH LOW GATE CHARGE STRUCTURE AND METHOD OF MAKING
    4.
    发明申请
    HIGH VOLTAGE TMOS SEMICONDUCTOR DEVICE WITH LOW GATE CHARGE STRUCTURE AND METHOD OF MAKING 有权
    具有低栅极电荷结构的高压TMOS半导体器件及其制造方法

    公开(公告)号:US20090108339A1

    公开(公告)日:2009-04-30

    申请号:US11932070

    申请日:2007-10-31

    IPC分类号: H01L29/78 H01L21/336

    摘要: A TMOS device (10) is formed using a semiconductor layer (16) of a first type. First and second regions (62,64) of the second type are formed in the semiconductor layer and are spaced apart. A third region (68) is formed in the semiconductor layer by implanting. The third region is between and contacts the first and second doped regions, is of the second conductivity type, and is less heavily doped than the first and second doped regions. A gate stack (67) is formed over a portion of the first doped region, a portion of the second doped region, and the third doped region. By implanting after forming the gate stack, fourth and fifth regions (98,100) of the first type are formed in interior portions of the first and second doped regions, respectively. The third region being of the same conductivity type as the first and second regions reduces Miller capacitance.

    摘要翻译: 使用第一类型的半导体层(16)形成TMOS器件(10)。 第二类型的第一和第二区域(62,64)形成在半导体层中并且间隔开。 通过注入在半导体层中形成第三区域(68)。 第三区域在第一和第二掺杂区域之间并且与第一和第二掺杂区域接触,具有第二导电类型,并且比第一和第二掺杂区域重掺杂。 栅极堆叠(67)形成在第一掺杂区域的一部分,第二掺杂区域的一部分和第三掺杂区域上。 通过在形成栅叠层之后注入,第一类型的第四和第五区(98,100)分别形成在第一和第二掺杂区的内部。 与第一和第二区域具有相同导电类型的第三区域减小了米勒电容。

    Power device termination structures and methods
    7.
    发明授权
    Power device termination structures and methods 有权
    功率器件端接结构和方法

    公开(公告)号:US09362394B2

    公开(公告)日:2016-06-07

    申请号:US14307678

    申请日:2014-06-18

    摘要: Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors.

    摘要翻译: 本文公开了功率器件端接结构和方法。 该结构包括沟槽栅极半导体器件。 沟槽栅极半导体器件包括半导体材料和沟槽栅极功率晶体管阵列。 阵列限定包括多个内部晶体管的内部区域和包括多个外部晶体管的外部区域。 内部晶体管包括具有平均内部区域间隔的多个内部沟槽。 外部晶体管包括具有平均端接区域间隔的多个外部沟槽。 平均端接区域间隔大于平均内部区域间隔,或者被选择为使得多个外部晶体管的击穿电压大于多个内部晶体管的击穿电压。

    POWER DEVICE TERMINATION STRUCTURES AND METHODS
    8.
    发明申请
    POWER DEVICE TERMINATION STRUCTURES AND METHODS 有权
    电力设备终止结构和方法

    公开(公告)号:US20150372130A1

    公开(公告)日:2015-12-24

    申请号:US14307678

    申请日:2014-06-18

    摘要: Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors.

    摘要翻译: 本文公开了功率器件端接结构和方法。 该结构包括沟槽栅极半导体器件。 沟槽栅极半导体器件包括半导体材料和沟槽栅极功率晶体管阵列。 阵列限定包括多个内部晶体管的内部区域和包括多个外部晶体管的外部区域。 内部晶体管包括具有平均内部区域间隔的多个内部沟槽。 外部晶体管包括具有平均端接区域间隔的多个外部沟槽。 平均端接区域间隔大于平均内部区域间隔,或者被选择为使得多个外部晶体管的击穿电压大于多个内部晶体管的击穿电压。

    Superjunction power MOSFET
    9.
    发明授权
    Superjunction power MOSFET 有权
    超结功率MOSFET

    公开(公告)号:US07378317B2

    公开(公告)日:2008-05-27

    申请号:US11304196

    申请日:2005-12-14

    IPC分类号: H01L21/336 H01L29/76

    摘要: Methods and apparatus are provided for TMOS devices, comprising multiple N-type source regions, electrically in parallel, located in multiple P-body regions separated by N-type JFET regions at a first surface. The gate overlies the body channel regions and the JFET region lying between the body regions. The JFET region communicates with an underlying drain region via an N-epi region. Ion implantation and heat treatment are used to tailor the net active doping concentration Nd in the JFET region of length Lacc and net active doping concentration Na in the P-body regions of length Lbody so that a charge balance relationship (Lbody*Na)=k1*(Lacc*Nd) between P-body and JFET regions is satisfied, where k1 is about 0.6≦k1≦1.4. The entire device can be fabricated using planar technology and the charge balanced regions need not extend through the underlying N-epi region to the drain.

    摘要翻译: 提供了用于TMOS器件的方法和装置,其包括并联的多个N型源极区域,位于在第一表面处由N型JFET区域分离的多个P体区域中。 栅极覆盖身体通道区域和位于身体区域之间的JFET区域。 JFET区域经由N-epi区域与下面的漏极区域连通。 离子注入和热处理用于定制长度为L的JFET区域中的净有源掺杂浓度N sub和净活性掺杂浓度N a, 在长度为L <! - SIPO - >本体的P体区域中,电荷平衡关系(L <! - SIPO - >) 满足P体和JFET区之间的> 1 *(L N N D D),其中k 1是约 0.6 <= K 1 <= 1.4。 整个器件可以使用平面技术制造,并且电荷平衡区域不需要延伸通过下面的N-epi区域到漏极。

    Power MOSFET current sense structure and method
    10.
    发明授权
    Power MOSFET current sense structure and method 有权
    功率MOSFET电流检测结构和方法

    公开(公告)号:US09293535B2

    公开(公告)日:2016-03-22

    申请号:US13610901

    申请日:2012-09-12

    摘要: A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET (304) to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.

    摘要翻译: 功率MOSFET具有主FET(MFET)和嵌入式电流感测FET(SFET)。 MFET栅极流道通过MFET和SFET之间的缓冲空间中的隔离栅极流道(IGR)耦合到SFET栅极流道。 在一个实施例中,n IGR(i = 1至n)将MFET(304)的第一部分的n + 1个栅极耦合到SFET的n个栅极。 IGR具有曲折的中心部分,其中每个SFET栅极流道经由IGR耦合到两个MFET栅极流道。 曲折的中心部分提供阻挡除了第一和最后一次IGR的外侧之外的所有IGR的SFET源和MFET源之间的寄生泄漏路径。 这些可能通过在围绕剩余泄漏路径的区域中增加体掺杂来阻止。 IGR基本上没有源区。