Invention Grant
US08031007B2 Error protection method, TDC module, CTDC module, all-digital phase-locked loop, and calibration method thereof
有权
误差保护方法，TDC模块，CTDC模块，全数字锁相环及其校准方法
- Patent Title: Error protection method, TDC module, CTDC module, all-digital phase-locked loop, and calibration method thereof
- Patent Title (中): 误差保护方法，TDC模块，CTDC模块，全数字锁相环及其校准方法
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Application No.: US12235624Application Date: 2008-09-23
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Publication No.: US08031007B2Publication Date: 2011-10-04
- Inventor: Hsiang-Hui Chang , Bing-Yu Hsieh , Jing-Hong Conan Zhan
- Applicant: Hsiang-Hui Chang , Bing-Yu Hsieh , Jing-Hong Conan Zhan
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: Mediatek Inc.
- Current Assignee: Mediatek Inc.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H03L7/085
- IPC: H03L7/085
Abstract:
An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.
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