A digital signal processor includes an up-sampling module that samples an input signal and generates up-sampling points. A natural sampling module includes a reference signal generation module that generates a reference signal. A crossing point detection module receives the up-sampling points and the reference signal and uses interpolation to detect intersection points of the input signal and the reference signal. The crossing point detection module determines values of the input signal at first and second evaluation times. The crossing point detection module estimates a current intersection point of the input signal and the reference signal as an intersection of the reference signal and a line that extends between first and second points on the input signal that correspond with the first and second evaluation times. A frequency of the reference signal is variable and a current switching period of the reference signal is not equal to a previous switching period.