Invention Grant
- Patent Title: Process for through silicon via filling
- Patent Title (中): 通过填充通过硅的工艺
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Application No.: US12762275Application Date: 2010-04-16
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Publication No.: US08043967B2Publication Date: 2011-10-25
- Inventor: Jonathan D. Reid , Katie Qun Wang , Mark J. Wiley
- Applicant: Jonathan D. Reid , Katie Qun Wang , Mark J. Wiley
- Applicant Address: US CA San Jose
- Assignee: Novellus Systems, Inc.
- Current Assignee: Novellus Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Weaver Austin Villeneuve & Sampson LLP
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.
Public/Granted literature
- US20100200412A1 Process For Through Silicon Via Filling Public/Granted day:2010-08-12
Information query
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