Invention Grant
- Patent Title: Wafer level vertical diode package structure and method for making the same
- Patent Title (中): 晶圆级垂直二极管封装结构及制作方法
-
Application No.: US12318876Application Date: 2009-01-12
-
Publication No.: US08053885B2Publication Date: 2011-11-08
- Inventor: Bily Wang , Sung-Yi Hsiao , Jack Chen
- Applicant: Bily Wang , Sung-Yi Hsiao , Jack Chen
- Applicant Address: TW Hsinchu
- Assignee: Harvatek Corporation
- Current Assignee: Harvatek Corporation
- Current Assignee Address: TW Hsinchu
- Agency: Rosenberg, Klein & Lee
- Main IPC: H01L23/485
- IPC: H01L23/485

Abstract:
A wafer level vertical diode package structure includes a first semiconductor layer, a second semiconductor layer, an insulative unit, a first conductive structure, and a second conductive structure. The second semiconductor layer is connected with one surface of the first semiconductor layer. The insulative unit is disposed around a lateral side of the first semiconductor layer and a lateral side of the second semiconductor layer. The first conductive structure is formed on a top surface of the first semiconductor layer and on one lateral side of the insulative layer. The second conductive structure is formed on a top surface of the second semiconductor layer and on another opposite lateral side of the insulative layer.
Public/Granted literature
- US20100176502A1 Wafer level vertical diode package structure and method for making the same Public/Granted day:2010-07-15
Information query
IPC分类: