Invention Grant
- Patent Title: Semiconductor package and manufacturing method thereof
- Patent Title (中): 半导体封装及其制造方法
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Application No.: US12535751Application Date: 2009-08-05
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Publication No.: US08053886B2Publication Date: 2011-11-08
- Inventor: Yuichi Taguchi , Mitsutoshi Higashi , Akinori Shiraishi , Hideaki Sakaguchi , Masahiro Sunohara
- Applicant: Yuichi Taguchi , Mitsutoshi Higashi , Akinori Shiraishi , Hideaki Sakaguchi , Masahiro Sunohara
- Applicant Address: JP Nagano
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano
- Agency: IPUSA, PLLC
- Priority: JP2008-207777 20080812; JP2008-328258 20081224
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A semiconductor package includes a wiring board and a semiconductor device mounted on the wiring board. At least one penetration hole extends from one surface of the semiconductor chip to an opposite surface of the semiconductor chip. A penetration electrode is situated inside the penetration hole without contacting a wall of the penetration hole. The penetration electrode has one end fixed to the one surface of the semiconductor chip and an opposite end protruding from the opposite surface of the semiconductor chip. A connection terminal is formed on the opposite end of the penetration electrode and electrically connected to the wiring board.
Public/Granted literature
- US20100038772A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2010-02-18
Information query
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