发明授权
- 专利标题: Phase interpolator for a timing signal generating circuit
- 专利标题(中): 用于定时信号发生电路的相位内插器
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申请号: US12358861申请日: 2009-01-23
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公开(公告)号: US08065553B2公开(公告)日: 2011-11-22
- 发明人: Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
- 申请人: Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
- 申请人地址: JP Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JP Kawasaki
- 代理机构: Arent Fox LLP
- 优先权: JP9-155429 19970612; JP10-002254 19980108; JP10-079401 19980326; JP10-135610 19980518
- 主分类号: G06F1/04
- IPC分类号: G06F1/04 ; G06F1/12 ; G06F1/24 ; H03J7/04
摘要:
A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
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