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22 条记录 (耗时 0.021 秒)

    Semiconductor device having a guard ring
    1.
    发明授权
    Semiconductor device having a guard ring 有权
    具有保护环的半导体器件

    公开(公告)号：US07256474B2

    公开(公告)日：2007-08-14

    申请号：US10777189

    申请日：2004-02-13

    申请人： Shigetoshi Wakayama ,  Mutsuaki Kai ,  Hiroyuki Kato ,  Masato Suga

    发明人： Shigetoshi Wakayama ,  Mutsuaki Kai ,  Hiroyuki Kato ,  Masato Suga

    IPC分类号： H01L23/544

    CPC分类号： H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A multilayer interconnection structure of a semiconductor device includes a first guard ring extending continuously along a periphery of a substrate and a second guard ring extending continuously in the multilayer interconnection structure along the periphery so as to be encircled by the first guard ring and so as to encircle an interconnection pattern inside the multilayer interconnection structure, wherein the first and second guard rings are connected with each other mechanically and continuously by a bridging conductor pattern extending continuously in a band form along a region including the first and second guard rings when viewed in the direction perpendicular to the substrate.

    摘要翻译： 半导体器件的多层互连结构包括沿着衬底的周边连续延伸的第一保护环和沿着周边在多层互连结构中连续延伸的第二保护环，以便被第一保护环包围，从而 围绕所述多层互连结构内部的互连图案，其中所述第一和第二保护环通过桥接导体图案彼此机械连续地连接，所述桥接导体图案沿着包括所述第一和第二保护环的区域以带状连续延伸， 垂直于衬底的方向。

    Destructive read type memory circuit, restoring circuit for the same and sense amplifier
    3.
    发明授权
    Destructive read type memory circuit, restoring circuit for the same and sense amplifier 有权

    公开(公告)号：US06205076B1

    公开(公告)日：2001-03-20

    申请号：US09276690

    申请日：1999-03-26

    申请人： Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Miyoshi Saito ,  Junji Ogawa

    发明人： Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Miyoshi Saito ,  Junji Ogawa

    IPC分类号： G11C700

    CPC分类号： G11C7/065 ,  G11C7/06 ,  G11C11/4091

    摘要： A restoring circuit 24, provided for each of the memory blocks 191 and 192, having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder 26. The present row address is held in one of the registers. When amplification is started by a sense amplifier 15, transfer gates 10 and 11 connected between the bit lines BL1 and *BL1 and the sense amplifier 15 are turned off to decrease the load of the sense amplifier 15, the amplified signal is stored in a buffer memory cell circuit 18, and accessing is completed with omitting restoring to the memory cell 12. While the memory cell block 191 is not selected, the data held in the buffer memory cell circuit 18 is stored into the memory cell row addressed by the content of the selected register. The sense amplifier 15 has PMOS and NMOS sense amplifiers. The PMOS sense amplifier, having a pair of cross-coupled PMOS transistors and a pair of transfer gates, the potential of the sources of the PMOS transistors being fixed at Vii, operates in a direct sensing mode when the transfer gates are off state, and then functions as a usual PMOS sense amplifier by turning on the transfer gates. Likewise for the NMOS sense amplifier.

    Semiconductor device including capacitor having decoupling capacity
    6.
    发明授权
    Semiconductor device including capacitor having decoupling capacity 失效
    包括具有去耦能力的电容器的半导体器件

    公开(公告)号：US07342434B2

    公开(公告)日：2008-03-11

    申请号：US11042090

    申请日：2005-01-26

    申请人： Shigetoshi Wakayama ,  Mutsuaki Kai

    发明人： Shigetoshi Wakayama ,  Mutsuaki Kai

    IPC分类号： G11C5/14

    CPC分类号： H03F3/45183 ,  H03F1/52 ,  H03F1/523 ,  H03F3/45475

    摘要： A capacitor has a MOS gate structure in which a gate insulating film is held between a gate terminal and a ground terminal as a dielectric. A switch unit is connected between the gate terminal and a power supply. The ground terminal is connected to a ground. A switch control circuit that switches a state of the switch unit between a conductive state and a nonconductive state is provided. A predetermined voltage and a voltage of the gate terminal are input to a non-inverting input terminal and an inverting input terminal of the switch control circuit, respectively. The switch unit is conductive when the voltage of the gate terminal is higher than the predetermined voltage, and nonconductive when the voltage of the gate terminal is lower than the predetermined voltage.

    摘要翻译： 电容器具有MOS栅极结构，其中栅极绝缘膜保持在栅极端子和接地端子之间作为电介质。 开关单元连接在栅极端子和电源之间。 接地端子接地。 提供了一种在导通状态和非导通状态之间切换开关单元的状态的开关控制电路。 栅极端子的预定电压和电压分别输入到开关控制电路的非反相输入端子和反相输入端子。 当栅极端子的电压高于预定电压时，开关单元导通，并且当栅极端子的电压低于预定电压时，开关单元导通。

    Semiconductor device
    8.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20060061409A1

    公开(公告)日：2006-03-23

    申请号：US11042090

    申请日：2005-01-26

    申请人： Shigetoshi Wakayama ,  Mutsuaki Kai

    发明人： Shigetoshi Wakayama ,  Mutsuaki Kai

    IPC分类号： G11C5/14

    CPC分类号： H03F3/45183 ,  H03F1/52 ,  H03F1/523 ,  H03F3/45475

    摘要： A capacitor has a MOS gate structure in which a gate insulating film is held between a gate terminal and a ground terminal as a dielectric. A switch unit is connected between the gate terminal and a power supply. The ground terminal is connected to a ground. A switch control circuit that switches a state of the switch unit between a conductive state and a nonconductive state is provided. A predetermined voltage and a voltage of the gate terminal are input to a non-inverting input terminal and an inverting input terminal of the switch control circuit, respectively. The switch unit is conductive when the voltage of the gate terminal is higher than the predetermined voltage, and nonconductive when the voltage of the gate terminal is lower than the predetermined voltage.

    摘要翻译： 电容器具有MOS栅极结构，其中栅极绝缘膜保持在栅极端子和接地端子之间作为电介质。 开关单元连接在栅极端子和电源之间。 接地端子接地。 提供了一种在导通状态和非导通状态之间切换开关单元的状态的开关控制电路。 栅极端子的预定电压和电压分别输入到开关控制电路的非反相输入端子和反相输入端子。 当栅极端子的电压高于预定电压时，开关单元导通，并且当栅极端子的电压低于预定电压时，开关单元导通。

    Destructive read type memory circuit, restoring circuit for the same and sense amplifier
    10.
    发明授权
    Destructive read type memory circuit, restoring circuit for the same and sense amplifier 有权
    破坏性读取型存储电路，恢复电路为相同和感测放大器

    公开(公告)号：US06333883B2

    公开(公告)日：2001-12-25

    申请号：US09768465

    申请日：2001-01-25

    申请人： Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Miyoshi Saito ,  Junji Ogawa

    发明人： Shigetoshi Wakayama ,  Kohtaroh Gotoh ,  Miyoshi Saito ,  Junji Ogawa

    IPC分类号： G11C700

    CPC分类号： G11C7/065 ,  G11C7/06 ,  G11C11/4091

    摘要： A restoring circuit 24, provided for each of the memory blocks 191 and 192, having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder 26. The present row address is held in one of the registers. When amplification is started by a sense amplifier 15, transfer gates 10 and 11 connected between the bit lines BL1 and *BL1 and the sense amplifier 15 are turned off to decrease the load of the sense amplifier 15, the amplified signal is stored in a buffer memory cell circuit 18, and accessing is completed with omitting restoring to the memory cell 12. While the memory cell block 191 is not selected, the data held in the buffer memory cell circuit 18 is stored into the memory cell row addressed by the content of the selected register. The sense amplifier 15 has PMOS and NMOS sense amplifiers. The PMOS sense amplifier, having a pair of cross-coupled PMOS transistors and a pair of transfer gates, the potential of the sources of the PMOS transistors being fixed at Vii, operates in a direct sensing mode when the transfer gates are off state, and then functions as a usual PMOS sense amplifier by turning on the transfer gates. Likewise for the NMOS sense amplifier.

    摘要翻译： 为每个存储器块191和192提供的恢复电路24具有寄存器和用于选择当前行地址和寄存器的输出之一的选择器，将选择器的输出提供给字解码器26.现在 行地址保存在其中一个寄存器中。 当由读出放大器15开始放大时，连接在位线BL1和* BL1与读出放大器15之间的传输门10和11被截止以减小读出放大器15的负载，放大的信号被存储在缓冲器 存储单元电路18，并且通过省略对存储单元12的恢复来完成访问。虽然没有选择存储单元块191，但是保持在缓冲存储单元电路18中的数据被存储到由 所选寄存器。 读出放大器15具有PMOS和NMOS读出放大器。 具有一对交叉耦合PMOS晶体管和一对传输栅极的PMOS读出放大器，PMOS晶体管的源极的电位固定在Vii处，当传输门断开时，其工作在直接感测模式，而 然后通过打开传输门来作为通常的PMOS读出放大器。 类似于NMOS读出放大器。