发明授权
- 专利标题： Lock detection circuit for phase locked loop
- 专利标题（中）： 锁相环锁定检测电路
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申请号： US12416933申请日： 2009-04-02
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公开(公告)号： US08076979B2公开(公告)日： 2011-12-13
- 发明人: Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
- 申请人： Manan Kathuria , Kumar Abhishek , Suhas Chakravarty , Suri Roopak
- 申请人地址： US TX Austin
- 专利权人： Freescale Semiconductor, Inc.
- 当前专利权人： Freescale Semiconductor, Inc.
- 当前专利权人地址： US TX Austin
- 代理商 Charles Bergere
- 优先权： IN896/DEL/2008 20080404
- 主分类号： H03J7/04
- IPC分类号： H03J7/04 ; H03L7/02
摘要：
A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.
公开/授权文献
- US20090251226A1 LOCK DETECTION CIRCUIT FOR PHASE LOCKED LOOP 公开/授权日：2009-10-08
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