公开(公告)号：US20130339761A1

公开(公告)日：2013-12-19

申请号：US13525347

申请日：2012-06-17

申请人： Kumar Abhishek ,  Manmohan Rana ,  Samaksh Sinha

发明人： Kumar Abhishek ,  Manmohan Rana ,  Samaksh Sinha

IPC分类号： G06F1/26

CPC分类号： G06F1/3287 ,  G06F1/3243 ,  H02J1/08 ,  H02J9/005 ,  H02J2001/008 ,  Y02D10/152 ,  Y02D50/20

摘要： A power management circuit for managing power supplied to an electronic circuit by a core power supply. The electronic circuit includes digital and analog circuit domains and operates in POWER-ON, RUN and STANDBY modes. The power management circuit includes a master state machine that exchanges a handshake signal with the analog circuit domain to monitor the modes of operation and generates first and second configuration signals. The power management circuit enables and disables the analog circuit domain based on the first and second configuration signals. A switch connected to the core power supply and the digital circuit module enables and disables the digital circuit domain based on the second configuration signal.

摘要翻译： 一种用于管理由核心电源供应到电子电路的电力的电源管理电路。 电子电路包括数字和模拟电路域，并在POWER-ON，RUN和STANDBY模式下工作。 电源管理电路包括主状态机，其与模拟电路域交换握手信号以监视操作模式并产生第一和第二配置信号。 电源管理电路基于第一和第二配置信号启用和禁用模拟电路域。 连接到核心电源和数字电路模块的开关基于第二配置信号启用和禁用数字电路域。

公开(公告)号：US20130093505A1

公开(公告)日：2013-04-18

申请号：US13275310

申请日：2011-10-17

申请人： Sunny Gupta ,  Kumar Abhishek ,  Garima Sharda ,  Samaksh Sinha

发明人： Sunny Gupta ,  Kumar Abhishek ,  Garima Sharda ,  Samaksh Sinha

IPC分类号： G05F1/10

CPC分类号： G05F1/575

摘要： A digital logic controller for regulating a voltage of a SoC includes a first input for receiving a reference signal having a first property that is constant over a range of operating conditions of the SoC, and a second input for receiving a second signal that has a second property that is indicative of an operating condition of the SoC. The second property may vary over a range of operating conditions of the SoC. A comparator compares the first and second properties and the digital logic controller, based on the comparison, outputs to a regulation signal to a voltage regulator to regulate the voltage of the SoC at or near a target voltage that is higher than a minimum operating voltage of the SoC.

摘要翻译： 用于调节SoC的电压的数字逻辑控制器包括用于接收具有在SoC的工作条件范围内恒定的第一特性的参考信号的第一输入端和用于接收第二信号的第二输入端 表示SoC的运行状况的属性。 第二个属性可能在SoC的一系列操作条件下变化。 比较器比较第一和第二特性和数字逻辑控制器，基于该比较，输出到调节信号到电压调节器，以调节在目标电压或其附近的目标电压的电压，该目标电压高于最低工作电压 SoC。

公开(公告)号：US20110199139A1

公开(公告)日：2011-08-18

申请号：US13097054

申请日：2011-04-29

申请人： Sunny ARORA ,  Kumar Abhishek ,  Mukesh Bansal ,  Shilpa Gupta

发明人： Sunny ARORA ,  Kumar Abhishek ,  Mukesh Bansal ,  Shilpa Gupta

IPC分类号： H03K3/289

CPC分类号： H03K3/356052 ,  H03K3/356121 ,  H03K3/356147

摘要： A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.

摘要翻译： 具有内部电平移位器的触发器电路包括输入级，时钟输入级，输出级和电平转换级。 输出级基于由输入级接收的输入信号和由时钟输入级接收的时钟信号产生输出信号。 电平移位级使输出信号的电压电平上升。

公开(公告)号：US07543205B2

公开(公告)日：2009-06-02

申请号：US11412532

申请日：2006-04-27

申请人： Kumar Abhishek

发明人： Kumar Abhishek

IPC分类号： G01R31/28 ,  H03K3/289

CPC分类号： G01R31/318594 ,  G01R31/31726

摘要： A system of control signal synchronization of a scannable storage circuit includes any number of storage circuits interconnected together with logic circuitry to form at least a portion of a functional circuit. Each of the storage circuits may include an input transmission gate to apply any one of a data input and a scan input to a storage element of the storage circuit based on an input circuitry that considers the state of the scan enable signal and a timing signal of a clock associated with the storage element. In addition, a control signal in a master latch of the storage element may synchronously close a hold loop in the master latch when the input transmission gate is opened upon the timing signal of the clock transitioning to a different state.

摘要翻译： 可扫描存储电路的控制信号同步的系统包括与逻辑电路互连在一起的任何数量的存储电路，以形成功能电路的至少一部分。 每个存储电路可以包括输入传输门，用于基于考虑扫描使能信号的状态的输入电路和数据输入和扫描输入的定时信号，将数据输入和扫描输入中的任一个应用于存储电路的存储元件 与存储元件相关联的时钟。 此外，当时钟转换到不同状态的定时信号打开输入传输门时，存储元件的主锁存器中的控制信号可以同步地闭合主锁存器中的保持环路。

公开(公告)号：US09383759B2

公开(公告)日：2016-07-05

申请号：US14509039

申请日：2014-10-07

申请人： Kumar Abhishek ,  Aniruddha Gupta ,  Sunny Gupta ,  Nitin Pant

发明人： Kumar Abhishek ,  Aniruddha Gupta ,  Sunny Gupta ,  Nitin Pant

IPC分类号： G05F1/46

CPC分类号： G05F1/462

摘要： An integrated circuit (IC) includes a digital-to-analog converter (DAC), a voltage monitoring circuit, and a controller. The voltage monitoring circuit includes low voltage detect (LVD) and low voltage warning (LVW) circuits that generate LVD and LVW reference voltage signals. The controller generates and stores a voltage margin word (a difference between first and second DAC words that correspond to the LVD and LVW reference voltage signals, respectively). The controller compares the voltage margin word with predetermined maximum and minimum voltage margin words. If the voltage margin word does not lie between the predetermined maximum and minimum voltage margin words, the controller generates a voltage trimming signal that scales the LVW reference voltage signal. After scaling, if the voltage margin word lies between the predetermined maximum and minimum voltage margin words, the controller generates a calibration pass signal, otherwise the controller generates a calibration fail signal.

摘要翻译： 集成电路（IC）包括数模转换器（DAC），电压监视电路和控制器。 电压监控电路包括产生LVD和LVW参考电压信号的低电压检测（LVD）和低电压警告（LVW）电路。 控制器产生并存储电压裕度字（分别对应于LVD和LVW参考电压信号的第一和第二DAC字之间的差异）。 控制器将电压裕度字与预定的最大和最小电压裕度字进行比较。 如果电压裕度字不在预定的最大和最小电压裕度字之间，则控制器产生缩放LVW参考电压信号的电压调整信号。 在缩放之后，如果电压裕度字位于预定的最大和最小电压裕度字之间，则控制器产生校准通过信号，否则控制器产生校准失败信号。

公开(公告)号：US09348346B2

公开(公告)日：2016-05-24

申请号：US14457129

申请日：2014-08-12

申请人： Kumar Abhishek ,  Siddi Jai Prakash ,  Kushal Kamal

发明人： Kumar Abhishek ,  Siddi Jai Prakash ,  Kushal Kamal

IPC分类号： G05F1/46

CPC分类号： G05F1/468

摘要： A voltage regulation subsystem for a microprocessor has both internal and external regulation modes. An internal auxiliary voltage regulator is selectively enabled to overdrive the voltage. The enablement of the auxiliary voltage regulator is contingent upon a comparison of bandgap references of the internal and external regulators used in the respective regulation modes, which boosts the supply voltage, enables circuitry supplied by the external regulator (with the assistance of auxiliary voltage regulators) to boot robustly in extreme Process-Voltage-Temperature (PVT) conditions.

摘要翻译： 微处理器的电压调节子系统具有内部和外部调节模式。 选择性地使能内部辅助电压调节器来过载驱动电压。 辅助电压调节器的启用取决于在各自调节模式下使用的内部和外部稳压器的带隙基准的比较，其提高了电源电压，使得由外部调节器提供的电路（在辅助电压调节器的辅助下） 在极端的过程电压 - 温度（PVT）条件下鲁棒启动。

公开(公告)号：US20150346272A1

公开(公告)日：2015-12-03

申请号：US14288358

申请日：2014-05-27

申请人： Kumar Abhishek ,  Kushal Kamal ,  Vandana Sapra

发明人： Kumar Abhishek ,  Kushal Kamal ,  Vandana Sapra

IPC分类号： G01R31/28

CPC分类号： G01R31/2856 ,  H03M1/1245 ,  H03M1/38 ,  H03M1/40 ,  H03M1/42 ,  H03M1/466

摘要： An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.

摘要翻译： 集成电路（IC）连接到具有弹簧针的自动测试设备（ATE）。 该IC包括模数转换器（ADC），压控振荡器（VCO）和补偿电路。 ATE通过弹簧引脚向ADC提供参考电压信号。 在pogo引脚上的电压降引起在ADC产生的数字信号中反映的参考电压信号中的误差。 VCO产生对应于参考电压信号的参考频率信号。 补偿电路接收参考频率信号和数字信号，并产生补偿因子信号。 补偿电路将补偿因子信号和数字信号相乘以产生补偿数字信号，以补偿由pogo引脚上的电位降引入的误差。

公开(公告)号：US08645886B2

公开(公告)日：2014-02-04

申请号：US13447305

申请日：2012-04-16

申请人： Kumar Abhishek ,  Benjamin J. Ehlers ,  Sunny Gupta ,  Stefano Pietri

发明人： Kumar Abhishek ,  Benjamin J. Ehlers ,  Sunny Gupta ,  Stefano Pietri

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/5036 ,  G06F2217/62 ,  G06F2217/78 ,  G06F2217/84

摘要： A method for verifying power management of an integrated circuit design includes estimating a current load requirement of clocked modules in the circuit design based on the clock frequency and a predefined current load model. The voltage supplied to the circuit design is monitored. A first voltage regulator provides additional current drive to the circuit design when the supplied voltage drops below a threshold value of a full throttle run mode of the circuit design. A second voltage regulator is enabled to boost a response time of the first voltage regulator when the voltage drops below the threshold value.

摘要翻译： 用于验证集成电路设计的电源管理的方法包括基于时钟频率和预定义的当前负载模型来估计电路设计中时钟模块的当前负载要求。 监测供应给电路设计的电压。 当所提供的电压低于电路设计的全油门运行模式的阈值时，第一电压调节器为电路设计提供额外的电流驱动。 当电压下降到阈值以下时，第二电压调节器能够升高第一电压调节器的响应时间。

公开(公告)号：US08487805B1

公开(公告)日：2013-07-16

申请号：US13403945

申请日：2012-02-23

申请人： Sunny Gupta ,  Kumar Abhishek ,  Kushal Kamal ,  Samaksh Sinha

发明人： Sunny Gupta ,  Kumar Abhishek ,  Kushal Kamal ,  Samaksh Sinha

IPC分类号： H03M1/34

CPC分类号： H03M1/007 ,  H03M1/46

摘要： An analog-to-digital converter (ADC) converts an analog input signal to a digital output signal by sampling an analog input signal to obtain an analog sample and then converting the analog sample to the digital output signal using a successive approximation algorithm. The method decreases ADC conversion time and increases ADC throughput.

摘要翻译： 模数转换器（ADC）通过采样模拟输入信号将模拟输入信号转换为数字输出信号，以获得模拟采样，然后使用逐次逼近算法将模拟采样转换为数字输出信号。 该方法可减少ADC转换时间并提高ADC吞吐量。

公开(公告)号：US08076979B2

公开(公告)日：2011-12-13

申请号：US12416933

申请日：2009-04-02

申请人： Manan Kathuria ,  Kumar Abhishek ,  Suhas Chakravarty ,  Suri Roopak

发明人： Manan Kathuria ,  Kumar Abhishek ,  Suhas Chakravarty ,  Suri Roopak

IPC分类号： H03J7/04 ,  H03L7/02

CPC分类号： H03L7/095 ,  Y10S331/02

摘要： A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.

摘要翻译： 用于检测参考信号和反馈信号之间的锁定状态的锁定检测器电路包括用于输出指示参考信号的时钟周期数的第一计数器值的第一计数器和用于输出指示的第二计数器值的第二计数器 的反馈信号的多个时钟周期。 异步比较器接收第一和第二计数器值，并提供具有与第一和第二计数器值之间的差成比例的脉冲宽度的输出信号。 脉冲宽度检测器接收比较器输出信号并产生指示比较器输出信号的脉冲宽度与预定阈值之间的关系的输出信号。 状态机根据脉冲宽度检测器输出信号控制至少一个锁定指示信号的状态。