发明授权
- 专利标题: Semiconductor device and method for manufacturing the same
- 专利标题(中): 半导体装置及其制造方法
-
申请号: US12478837申请日: 2009-06-05
-
公开(公告)号: US08084869B2公开(公告)日: 2011-12-27
- 发明人: Takashi Miwa , Michiaki Sugiyama , Kazumasa Yanagisawa
- 申请人: Takashi Miwa , Michiaki Sugiyama , Kazumasa Yanagisawa
- 申请人地址: JP Kawasaki-shi
- 专利权人: Renesas Electronics Corporation
- 当前专利权人: Renesas Electronics Corporation
- 当前专利权人地址: JP Kawasaki-shi
- 代理机构: Miles & Stockbridge P.C.
- 优先权: JP2008-189663 20080723
- 主分类号: H01L23/29
- IPC分类号: H01L23/29
摘要:
A technique permitting the reduction in size of a semiconductor device is provided. In a BGA type semiconductor device with a semiconductor chip flip-chip-bonded onto a wiring substrate, bump electrodes of the semiconductor chip are coupled to lands formed at an upper surface of the wiring substrate. The lands at the upper surface of the wiring substrate are coupled electrically to solder balls formed on a lower surface of the wiring substrate. Therefore, the lands include first type lands with lead-out lines coupled thereto and second type lands with lead-out lines not coupled thereto but with vias formed just thereunder. The lands are arrayed in six or more rows at equal pitches in an advancing direction of the rows. However, a row-to-row pitch is not made an equal pitch. In land rows which are likely to cause a short-circuit, the pitch between adjacent rows is made large, while in land rows which are difficult to cause a short-circuit, the pitch between adjacent rows is made small. By so doing, both prevention of a short-circuit and improvement of the layout density of lands are attained at a time.