发明授权
- 专利标题: Arithmetic processing apparatus
- 专利标题(中): 算术处理装置
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申请号: US11720899申请日: 2005-08-24
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公开(公告)号: US08086830B2公开(公告)日: 2011-12-27
- 发明人: Takeshi Furuta , Hideshi Nishida , Takeshi Tanaka
- 申请人: Takeshi Furuta , Hideshi Nishida , Takeshi Tanaka
- 申请人地址: JP Osaka
- 专利权人: Panasonic Corporation
- 当前专利权人: Panasonic Corporation
- 当前专利权人地址: JP Osaka
- 代理机构: Greenblum & Bernstein, P.L.C.
- 优先权: JP2005-104107 20050331
- 国际申请: PCT/JP2005/015361 WO 20050824
- 国际公布: WO2006/112045 WO 20061026
- 主分类号: G06F15/80
- IPC分类号: G06F15/80 ; G06F9/302 ; G06F9/305
摘要:
An arithmetic processing apparatus capable of performing an arithmetic operation for generating a condition flag commonly referred to by using a condition flag generated on an arithmetic operation unit basis in as few steps as possible is provided. The arithmetic processing apparatus, which processes multiple data in parallel based on single instruction, includes: processing elements capable of performing a common arithmetic operation based on the evaluation result of the instruction stored in the instruction register; and a condition flag arithmetic operation unit capable of performing one of the logical operation and the comparison operation on the condition flag retained in each processing element, transferring the operation result to each processing element, and updating the condition flag based on the operation result.
公开/授权文献
- US20090228691A1 ARITHMETIC PROCESSING APPARATUS 公开/授权日:2009-09-10