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344 条记录 (耗时 0.037 秒)

    Vector logical operation and test instructions with result negation
    1.
    发明授权
    Vector logical operation and test instructions with result negation 有权

    公开(公告)号：US11593105B2

    公开(公告)日：2023-02-28

    申请号：US16236439

    申请日：2018-12-29

    申请人： Intel Corporation

    发明人： ElMoustapha Ould-Ahmed-Vall

    IPC分类号： G06F9/305 ,  G06F9/30

    摘要： Systems, methods, and apparatuses relating to performing logical operations on packed data elements and testing the results of that logical operation to generate a packed data resultant are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, the instruction having fields that identify a first packed data source, a second packed data source, and a packed data destination, and an opcode that indicates a bitwise logical operation to perform on the first packed data source and the second packed data source and indicates a width of each element of the first packed data source and the second packed data source; and an execution circuit to execute the decoded instruction to perform the bitwise logical operation indicated by the opcode on the first packed data source and the second packed data source to produce a logical operation result of packed data elements having a same width as the width indicated by the opcode, perform a test operation on each element of the logical operation result to set a corresponding bit in a packed data test operation result to a first value when any of the bits in a respective element of the logical operation result are set to the first value, and set the corresponding bit to a second value otherwise, and store the packed data test operation result into the packed data destination.

    Integrating sign extensions for loads
    2.
    发明授权
    Integrating sign extensions for loads 有权

    公开(公告)号：US10126976B2

    公开(公告)日：2018-11-13

    申请号：US15436138

    申请日：2017-02-17

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Michael K. Gschwind

    IPC分类号： G06F9/302 ,  G06F9/305 ,  G06F9/312 ,  G06F3/06 ,  G06F12/0875 ,  G06F9/30 ,  G06F7/499

    摘要： An address and a data size are provided to a rotator. The rotator stores, based on the address and the data size, a data element in a location having a defined number of positions. The data element includes one or more data units and the one or more data units are aligned correctly in one or more positions of the location based on a predefined position in the location to receive a selected data unit of the one or more data units. The rotator replicates a value of a chosen data unit of the one or more data units to one or more other positions of the location.

    Fast and compact circuit for bus inversion
    7.
    发明授权
    Fast and compact circuit for bus inversion 失效
    快速紧凑的电路用于总线反相

    公开(公告)号：US08713298B2

    公开(公告)日：2014-04-29

    申请号：US13361291

    申请日：2012-01-30

    申请人： Mayur Joshi

    发明人： Mayur Joshi

    IPC分类号： G06F11/00 ,  G06F9/305 ,  G06F13/20

    CPC分类号： G06F13/4217 ,  G06F7/501 ,  Y02D10/14 ,  Y02D10/151

    摘要： A processor based system with at least one processor, at least one memory controller and optionally other devices having bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.

    摘要翻译： 一种基于处理器的系统，具有至少一个处理器，至少一个存储器控制器以及可选的其它设备，其具有在负责总线反转决定的电路中具有快速且紧凑的多数选民的总线系统。 多数选民在具有两个分支的模拟电路中实现。 一个分支总结了在不反转的情况下发送比特的优点，另外一个总结了利用反演发送比特的优点。 多数选民通过同时比较每个分支中的当前驱动器来计算略微多于一个门延迟的总线反转决定。

    Processing vectors using wrapping negation instructions in the macroscalar architecture
    8.
    发明授权
    Processing vectors using wrapping negation instructions in the macroscalar architecture 有权
    在宏观架构中使用包装否定指令处理向量

    公开(公告)号：US08583904B2

    公开(公告)日：2013-11-12

    申请号：US13628781

    申请日：2012-09-27

    申请人： Apple Inc.

    发明人： Jeffry E. Gonion

    IPC分类号： G06F9/302 ,  G06F9/305

    CPC分类号： G06F8/4441 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30072

    摘要： Embodiments of a system and a method in which a processor may execute instructions that cause the processor to receive an input vector and a control vector are disclosed. The executed instructions may also cause the processor to perform a negation operation dependent upon the input vector and the control vector.

    摘要翻译： 公开了一种系统和方法的实施例，其中处理器可以执行使处理器接收输入向量和控制向量的指令。 执行的指令还可以使处理器执行取决于输入向量和控制向量的否定操作。

    METHOD AND APPARATUS FOR GENERATING FLAGS FOR A PROCESSOR
    9.
    发明申请
    METHOD AND APPARATUS FOR GENERATING FLAGS FOR A PROCESSOR 有权
    用于生成加工商标签的方法和装置

    公开(公告)号：US20130166889A1

    公开(公告)日：2013-06-27

    申请号：US13334286

    申请日：2011-12-22

    申请人： Srikanth Arekapudi ,  Saurabh Gupta

    发明人： Srikanth Arekapudi ,  Saurabh Gupta

    IPC分类号： G06F9/315 ,  G06F9/302 ,  G06F9/305 ,  G06F9/38

    CPC分类号： G06F9/30094 ,  G06F9/30032

    摘要： A method and apparatus are described for generating flags in response to processing data during an execution pipeline cycle of a processor. The processor may include a multiplexer configured generate valid bits for received data according to a designated data size, and a logic unit configured to control the generation of flags based on a shift or rotate operation command, the designated data size and information indicating how many bytes and bits to rotate or shift the data by. A carry flag may be used to extend the amount of bits supported by shift and rotate operations. A sign flag may be used to indicate whether a result is a positive or negative number. An overflow flag may be used to indicate that a data overflow exists, whereby there are not a sufficient number of bits to store the data.

    摘要翻译： 描述了用于在处理器的执行流水线循环期间响应于处理数据生成标志的方法和装置。 处理器可以包括多路复用器，其被配置为根据指定的数据大小为接收的数据生成有效位，以及逻辑单元，被配置为基于移位或旋转操作命令来控制标志的生成，所指定的数据大小和指示多少字节的信息 以及用于旋转或移动数据的位。 可以使用进位标志来扩展由移位和旋转操作支持的位数。 符号标志可以用于指示结果是正数还是负数。 可以使用溢出标志来指示存在数据溢出，从而没有足够数量的位来存储数据。

    FINE-GRAINED PRIVILEGE ESCALATION
    10.
    发明申请
    FINE-GRAINED PRIVILEGE ESCALATION 失效
    精细化的特权自治

    公开(公告)号：US20120151185A1

    公开(公告)日：2012-06-14

    申请号：US12967085

    申请日：2010-12-14

    申请人： Anthony J. Bybell ,  Anup Wadia

    发明人： Anthony J. Bybell ,  Anup Wadia

    IPC分类号： G06F9/318 ,  G06F9/312 ,  G06F9/305

    CPC分类号： G06F9/30189 ,  G06F9/30076 ,  G06F9/3802 ,  G06F9/382

    摘要： A processor and a method for privilege escalation in a processor are provided. The method may comprise fetching an instruction from a fetch address, where the instruction requires the processor to be in supervisor mode for execution, and determining whether the fetch address is within a predetermined address range. The instruction is filtered through an instruction mask and then it is determined whether the instruction, after being filtered through the mask, equals the value in an instruction value compare register. The processor privilege is raised to supervisor mode for execution of the instruction in response to the fetch address being within the predetermined address range and the filtered instruction equaling the value in the instruction value compare register, wherein the processor privilege is raised to supervisor mode without use of an interrupt. The processor privilege returns to its previous level after execution of the instruction.

    摘要翻译： 提供了一种用于处理器中的特权升级的处理器和方法。 该方法可以包括从获取地址获取指令，其中指令要求处理器处于监控模式以执行，以及确定获取地址是否在预定地址范围内。 指令通过指令屏蔽过滤，然后确定在通过掩码滤波后的指令是否等于指令值比较寄存器中的值。 处理器特权被提升到管理员模式，以响应于提取地址在预定地址范围内执行指令，并且滤波指令等于指令值比较寄存器中的值，其中处理器特权被提升到管理员模式而不使用 的中断。 执行指令后，处理器权限返回到上一级。