发明授权
- 专利标题: Semiconductor integrated circuit device for scan testing
- 专利标题(中): 半导体集成电路器件进行扫描测试
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申请号: US12256535申请日: 2008-10-23
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公开(公告)号: US08086889B2公开(公告)日: 2011-12-27
- 发明人: Yuichi Ito , Yasuhiro Fujimura , Koki Tsutsumida , Shigeru Nakahara
- 申请人: Yuichi Ito , Yasuhiro Fujimura , Koki Tsutsumida , Shigeru Nakahara
- 申请人地址: JP Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JP Tokyo
- 代理机构: Miles & Stockbridge P.C.
- 优先权: JP2007-278308 20071026
- 主分类号: G06F1/04
- IPC分类号: G06F1/04 ; G01R31/28
摘要:
A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.
公开/授权文献
- US20090113230A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 公开/授权日:2009-04-30
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