Invention Grant
- Patent Title: Method of forming self-aligned low resistance contact layer
- Patent Title (中): 形成自对准低电阻接触层的方法
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Application No.: US12228386Application Date: 2008-08-11
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Publication No.: US08088665B2Publication Date: 2012-01-03
- Inventor: Willy Rachmady , Jason W. Klaus , Ravi Pillarisetty , Niloy Mukherjee , Jack Kavalieros , Sean King
- Applicant: Willy Rachmady , Jason W. Klaus , Ravi Pillarisetty , Niloy Mukherjee , Jack Kavalieros , Sean King
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle, PLLC
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
Embodiments of the present invention describe a method of fabricating low resistance contact layers on a semiconductor device. The semiconductor device comprises a substrate having source and drain regions. The substrate is alternatingly exposed to a first precursor and a second precursor to selectively deposit an amorphous semiconductor layer onto each of the source and drain regions. A metal layer is then deposited over the amorphous semiconductor layer on each of the source and drain regions. An annealing process is then performed on the substrate to allow the metal layer to react with amorphous semiconductor layer to form a low resistance contact layer on each of the source and drain regions. The low resistance contact layer on each of the source and drain regions can be formed as either a silicide layer or germanide layer depending on the type of precursors used.
Public/Granted literature
- US20100035399A1 Method of forming self-aligned low resistance contact layer Public/Granted day:2010-02-11
Information query
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