Invention Grant
US08088683B2 Sequential deposition and anneal of a dielectic layer in a charge trapping memory device
有权
在电荷俘获存储器件中的介电层的顺序沉积和退火
- Patent Title: Sequential deposition and anneal of a dielectic layer in a charge trapping memory device
- Patent Title (中): 在电荷俘获存储器件中的介电层的顺序沉积和退火
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Application No.: US12080166Application Date: 2008-03-31
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Publication No.: US08088683B2Publication Date: 2012-01-03
- Inventor: Krishnaswamy Ramkumar , Sagy Levy
- Applicant: Krishnaswamy Ramkumar , Sagy Levy
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 or ND3 ambient followed by an N2O or NO ambient. In one embodiment, such a method is employed to form a dielectric layer having a stoichiometry attainable with only a deposition process but with a uniform material quality uncharacteristically high of a deposition process. In particular embodiments, sequential deposition-anneal operations provide an annealed first dielectric layer upon which a second dielectric layer may be left substantially non-annealed.
Public/Granted literature
- US20090243001A1 Sequential deposition and anneal of a dielectic layer in a charge trapping memory device Public/Granted day:2009-10-01
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