OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS
    1.
    发明申请
    OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS 有权
    具有多个氧化物层的氧化物 - 氮氧化物堆

    公开(公告)号:US20130175504A1

    公开(公告)日:2013-07-11

    申请号:US13436872

    申请日:2012-03-31

    IPC分类号: H01L29/775

    摘要: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

    摘要翻译: 描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。 通常,该器件包括由半导体材料形成的沟道,该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层,其在所述隧道氧化物层上包含富氧的第一氧氮化物层,其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱,并且将贫氧的第二氮氧化物层置于 第一氧氮化物层,其中第二氧氮化物层的化学计量组成导致其陷阱致密。 在一个实施例中,该器件包括非平面晶体管,其包括具有邻接通道的多个表面的栅极,并且栅极包括隧道氧化物层和多层电荷存储层。

    Trapped-charge non-volatile memory with uniform multilevel programming
    2.
    发明授权
    Trapped-charge non-volatile memory with uniform multilevel programming 有权
    具有均匀多电平编程的陷阱充电非易失性存储器

    公开(公告)号:US07898852B1

    公开(公告)日:2011-03-01

    申请号:US12005803

    申请日:2007-12-27

    IPC分类号: G11C16/04

    摘要: Methods and apparatus for programming and sensing a bi-nitride layer trapped-charge memory device in one of a first and second programmed states or one of a first and second erased states, where the first and second programmed states correspond to first and second uniform trapped charge distributions of a first charge type and the first and second erased states correspond to first and second uniform trapped charge distributions of a second charge type.

    摘要翻译: 用于以第一和第二编程状态或第一和第二擦除状态中的一种编程和感测二氮化物层捕获电荷存储器件的方法和装置,其中第一和第二编程状态对应于第一和第二均匀捕获 第一充电类型和第一和第二擦除状态的电荷分布对应于第二充电类型的第一和第二均匀俘获电荷分布。

    Single-wafer process for fabricating a nonvolatile charge trap memory device
    3.
    发明授权
    Single-wafer process for fabricating a nonvolatile charge trap memory device 有权
    用于制造非易失性电荷陷阱存储器件的单晶片工艺

    公开(公告)号:US07670963B2

    公开(公告)日:2010-03-02

    申请号:US11904513

    申请日:2007-09-26

    IPC分类号: H01L21/469

    摘要: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.

    摘要翻译: 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括首先在单晶片簇工具的第一处理室中的衬底上形成隧道电介质层。 然后在单晶片簇工具的第二处理室中的隧道介电层上形成电荷捕获层。 然后在单晶片簇工具的第二或第三处理室中的电荷俘获层上形成顶部电介质层。

    Sequential deposition and anneal of a dielectic layer in a charge trapping memory device
    4.
    发明申请
    Sequential deposition and anneal of a dielectic layer in a charge trapping memory device 有权
    在电荷俘获存储器件中的介电层的顺序沉积和退火

    公开(公告)号:US20090243001A1

    公开(公告)日:2009-10-01

    申请号:US12080166

    申请日:2008-03-31

    IPC分类号: H01L29/00 H01L21/31

    CPC分类号: H01L21/28282 H01L21/3145

    摘要: Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 or ND3 ambient followed by an N2O or NO ambient. In one embodiment, such a method is employed to form a dielectric layer having a stoichiometry attainable with only a deposition process but with a uniform material quality uncharacteristically high of a deposition process. In particular embodiments, sequential deposition-anneal operations provide an annealed first dielectric layer upon which a second dielectric layer may be left substantially non-annealed.

    摘要翻译: 重复沉积和退火操作以将沉积破坏成多个顺序的沉积退火操作以达到期望的退火介电层厚度。 在一个具体实施方案中,进行包括NH 3或ND 3环境,随后是N 2 O或NO环境的两步退火。 在一个实施例中,采用这种方法形成具有仅通过沉积工艺可获得的化学计量但具有均匀材料质量的电介质层,这在沉积过程中具有非常高的特性。 在特定实施例中,顺序沉积 - 退火操作提供退火的第一介电层,第二介电层可以在其上基本上保持不退火。

    Oxide-nitride-oxide stack having multiple oxynitride layers
    6.
    发明授权
    Oxide-nitride-oxide stack having multiple oxynitride layers 有权
    具有多个氮氧化物层的氧化物 - 氮化物 - 氧化物堆叠

    公开(公告)号:US09449831B2

    公开(公告)日:2016-09-20

    申请号:US13436872

    申请日:2012-03-31

    摘要: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

    摘要翻译: 描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。 通常,该器件包括由半导体材料形成的沟道,该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层,其在所述隧道氧化物层上包含富氧的第一氧氮化物层,其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱,并且将贫氧的第二氮氧化物层置于 第一氧氮化物层,其中第二氧氮化物层的化学计量组成导致其陷阱致密。 在一个实施例中,该器件包括非平面晶体管,其包括具有邻接通道的多个表面的栅极,并且栅极包括隧道氧化物层和多层电荷存储层。

    SONOS ONO stack scaling
    7.
    发明授权
    SONOS ONO stack scaling 有权
    SONOS ONO堆栈缩放

    公开(公告)号:US09299568B2

    公开(公告)日:2016-03-29

    申请号:US13539461

    申请日:2012-07-01

    摘要: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

    摘要翻译: 提供了一种缩放非易失性俘获电荷存储器件及其制造的器件的方法。 在一个实施例中,该方法包括形成包括电连接衬底中的源极区域和漏极区域的多晶硅沟道区域。 通过氧化衬底以在沟道区域上的衬底上形成隧穿层以形成氧化膜并氮化氧化膜。 在隧道层上形成包含富氧的第一层和无氧的第二层的多层电荷俘获层,以及沉积在多层电荷俘获层上的阻挡层。 在一个实施方案中,该方法还包括稀释的湿氧化以致密集沉积的阻塞氧化物并氧化贫氧的第二层的一部分。

    NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION
    9.
    发明申请
    NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION 有权
    具有高介电常数阻塞区域的非挥发性电荷捕获存储器件

    公开(公告)号:US20130175604A1

    公开(公告)日:2013-07-11

    申请号:US13436875

    申请日:2012-03-31

    IPC分类号: H01L29/792

    摘要: An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

    摘要翻译: 描述了非易失性电荷陷阱存储器件的实施例。 在一个实施例中,该装置包括一个通道,该沟道包括覆盖在电连接存储器件的第一扩散区和第二扩散区的衬底上的表面的硅以及与沟道的至少一部分相交并且覆盖的栅极堆,栅极 包括邻接通道的隧道氧化物的堆叠,邻接隧道氧化物的分裂电荷捕获区域和与分离的电荷捕获区域邻接的多层阻挡电介质。 分离电荷捕获区域包括第一电荷捕获层,其包含更接近隧道氧化物的氮化物,以及包含覆盖在第一电荷俘获层上的氮化物的第二电荷俘获层。 多层阻挡电介质至少包括高K电介质层。