Invention Grant
- Patent Title: Three-dimensional integrated circuit stacking-joint interface structure
- Patent Title (中): 三维集成电路堆叠接口结构
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Application No.: US12259879Application Date: 2008-10-28
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Publication No.: US08097953B2Publication Date: 2012-01-17
- Inventor: Ming-Hong Tseng , Kai-Ming Ching , Chen-Shien Chen , Ching-Wen Hsiao , Hon-Lin Huang , Tsung-Ding Wang
- Applicant: Ming-Hong Tseng , Kai-Ming Ching , Chen-Shien Chen , Ching-Wen Hsiao , Hon-Lin Huang , Tsung-Ding Wang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, LLP
- Main IPC: H01L23/52
- IPC: H01L23/52
Abstract:
A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV.
Public/Granted literature
- US20100102453A1 Three-Dimensional Integrated Circuit Stacking-Joint Interface Structure Public/Granted day:2010-04-29
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