Invention Grant
US08099533B2 Controller and a method for controlling the communication between a processor and external peripheral device 有权
控制器和用于控制处理器和外部外围设备之间的通信的方法

  • Patent Title: Controller and a method for controlling the communication between a processor and external peripheral device
  • Patent Title (中): 控制器和用于控制处理器和外部外围设备之间的通信的方法
  • Application No.: US11573194
    Application Date: 2005-07-22
  • Publication No.: US08099533B2
    Publication Date: 2012-01-17
  • Inventor: Chee Yu NgNitin Satishchandra Kabra
  • Applicant: Chee Yu NgNitin Satishchandra Kabra
  • Applicant Address: NL Eindhoven
  • Assignee: NXP B.V.
  • Current Assignee: NXP B.V.
  • Current Assignee Address: NL Eindhoven
  • Priority: EP04103727 20040803
  • International Application: PCT/IB2005/052477 WO 20050722
  • International Announcement: WO2006/016298 WO 20060216
  • Main IPC: G06F3/00
  • IPC: G06F3/00 G06F13/12 G06F15/00
Controller and a method for controlling the communication between a processor and external peripheral device
Abstract:
The present invention relates to a data processing system based on a multithreaded operating system. The data processing system comprises at least one processor (PROC) for processing data based on multiple threads, at least one controller unit (CU) for controlling the communication between said at least one processor (PROC) and an external peripheral device (PD) connected to said at least one controller unit (CU). Said at least one controller unit (CU) comprises at least one buffer memory (BM) for buffering data from said peripheral device (PD) connected to said at least one controller unit (CU), and at least one memory managing unit (MMU) for managing the access to said at least one buffer memory (BM) by mapping said at least one buffer memory (BM) into N banks (C0-C3) each with a dedicated prefetch register (Addr.0-Addr.3). At least one of said multiple threads (T0-T3) is mapped to one of said N banks (C0-C3) and its dedicated prefetch register (Addr.0-Addr.3).
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