公开(公告)号：US08099533B2

公开(公告)日：2012-01-17

申请号：US11573194

申请日：2005-07-22

Applicant: Chee Yu Ng ,  Nitin Satishchandra Kabra

Inventor： Chee Yu Ng ,  Nitin Satishchandra Kabra

IPC: G06F3/00 ,  G06F13/12 ,  G06F15/00

CPC classification number: G06F13/4059 ,  G06F9/383 ,  G06F9/3851

Abstract: The present invention relates to a data processing system based on a multithreaded operating system. The data processing system comprises at least one processor (PROC) for processing data based on multiple threads, at least one controller unit (CU) for controlling the communication between said at least one processor (PROC) and an external peripheral device (PD) connected to said at least one controller unit (CU). Said at least one controller unit (CU) comprises at least one buffer memory (BM) for buffering data from said peripheral device (PD) connected to said at least one controller unit (CU), and at least one memory managing unit (MMU) for managing the access to said at least one buffer memory (BM) by mapping said at least one buffer memory (BM) into N banks (C0-C3) each with a dedicated prefetch register (Addr.0-Addr.3). At least one of said multiple threads (T0-T3) is mapped to one of said N banks (C0-C3) and its dedicated prefetch register (Addr.0-Addr.3).

Abstract translation: 本发明涉及一种基于多线程操作系统的数据处理系统。 数据处理系统包括用于基于多个线程处理数据的至少一个处理器（PROC），用于控制所述至少一个处理器（PROC）和连接的外部外围设备（PD）之间的通信的至少一个控制器单元（CU） 到所述至少一个控制器单元（CU）。 所述至少一个控制器单元（CU）包括用于缓冲来自连接到所述至少一个控制器单元（CU）的所述外围设备（PD）的数据的至少一个缓冲存储器（BM），以及至少一个存储器管理单元（MMU） 用于通过将所述至少一个缓冲存储器（BM）映射成具有专用预取寄存器（Addr.0-Addr.3）的N个存储体（C0-C3）来管理对所述至少一个缓冲存储器（BM）的访问。 所述多个线程（T0-T3）中的至少一个映射到所述N个存储体（C0-C3）和其专用预取寄存器（Addr.0-Addr.3）中的一个。