发明授权
- 专利标题： Methods of fabricating transistors including self-aligned gate electrodes and source/drain regions
- 专利标题（中）： 制造晶体管的方法包括自对准栅电极和源/漏区
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申请号： US12509855申请日： 2009-07-27
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公开(公告)号： US08105889B2公开(公告)日： 2012-01-31
- 发明人: R. Peter Smith , Scott T. Sheppard
- 申请人： R. Peter Smith , Scott T. Sheppard
- 申请人地址： US NC Durham
- 专利权人： Cree, Inc.
- 当前专利权人： Cree, Inc.
- 当前专利权人地址： US NC Durham
- 代理机构： Myers Bigel Sibley & Sajovec
- 主分类号： H01L21/338
- IPC分类号： H01L21/338
摘要：
Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a masking gate on the protective layer. The masking gate includes an upper portion having a width that is larger than a width of the via hole and having a lower portion extending into the via hole. The methods further include implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask.
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