Invention Grant
- Patent Title: Laminated silicon gate electrode
- Patent Title (中): 层压硅栅电极
-
Application No.: US11041178Application Date: 2005-01-24
-
Publication No.: US08115263B2Publication Date: 2012-02-14
- Inventor: Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
- Applicant: Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Tung & Associates
- Main IPC: H01L29/78
- IPC: H01L29/78
Abstract:
Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.
Public/Granted literature
- US20050121671A1 Method for fabricating laminated silicon gate electrode Public/Granted day:2005-06-09
Information query
IPC分类:
