To provide a semiconductor integrated circuit including: a detection circuit that detects an occurrence of latch up and can be configured while adopting a layout configuration that suppresses the occurrence of latch up; and a recovery unit that enables a recovery from the latch up without cutting off a positive potential. The semiconductor integrated circuit includes: a n-channel MOS transistor 7 that is formed on a P-type region 3 on a semiconductor substrate; and a latch up detection circuit that detects an occurrence of latch up in the n-channel MOS transistor 7. The latch up detection circuit includes: a n-MOS transistor structure 12 in which a source 10 and a back gate 8 are connected in common with a source 5 and the back gate 8 of the n-channel MOS transistor 7; and an electric current detection unit 15 that detects an electric current flowing to a drain 9 of the n-MOS transistor structure 12.