Invention Grant
US08120065B2 Tensile strained NMOS transistor using group III-N source/drain regions
有权
使用III-N族源/漏区的拉伸应变NMOS晶体管
- Patent Title: Tensile strained NMOS transistor using group III-N source/drain regions
- Patent Title (中): 使用III-N族源/漏区的拉伸应变NMOS晶体管
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Application No.: US12541763Application Date: 2009-08-14
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Publication No.: US08120065B2Publication Date: 2012-02-21
- Inventor: Suman Datta , Justin K. Brask , Been-Yih Jin , Jack T. Kavalieros , Mantu K. Hudait
- Applicant: Suman Datta , Justin K. Brask , Been-Yih Jin , Jack T. Kavalieros , Mantu K. Hudait
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/02
- IPC: H01L21/02
Abstract:
Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.
Public/Granted literature
- US20090302350A1 Tensile Strained NMOS Transistor Using Group III-N Source/Drain Regions Public/Granted day:2009-12-10
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