发明授权
US08125837B2 Semiconductor memory device with read/write margin control using back-gate bias
有权
具有读/写裕度控制的半导体存储器件使用背栅极偏置
- 专利标题: Semiconductor memory device with read/write margin control using back-gate bias
- 专利标题(中): 具有读/写裕度控制的半导体存储器件使用背栅极偏置
-
申请号: US12543499申请日: 2009-08-18
-
公开(公告)号: US08125837B2公开(公告)日: 2012-02-28
- 发明人: Masanao Yamaoka , Kenichi Osada
- 申请人: Masanao Yamaoka , Kenichi Osada
- 申请人地址: JP Kawasaki-shi
- 专利权人: Renesas Electronics Corporation
- 当前专利权人: Renesas Electronics Corporation
- 当前专利权人地址: JP Kawasaki-shi
- 代理机构: Miles & Stockbridge P.C.
- 优先权: JP2008-223290 20080901
- 主分类号: G11C11/00
- IPC分类号: G11C11/00 ; G11C7/10 ; G11C5/14
摘要:
The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.
公开/授权文献
- US20100054049A1 SEMICONDUCTOR DEVICE 公开/授权日:2010-03-04
信息查询