Double quantum well structures for transistors are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a first quantum well channel coupled with the first barrier layer wherein the first quantum well channel includes a group III-V semiconductor material or a group II-VI semiconductor material, or combinations thereof, a second barrier layer coupled to the first quantum well channel, and a second quantum well channel coupled to the barrier layer wherein the second quantum well channel includes a group III-V semiconductor material or a group II-VI semiconductor material, or combinations thereof.