发明授权
- 专利标题: Dynamic critical path detector for digital logic circuit paths
- 专利标题(中): 用于数字逻辑电路路径的动态关键路径检测器
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申请号: US11937111申请日: 2007-11-08
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公开(公告)号: US08132136B2公开(公告)日: 2012-03-06
- 发明人: Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
- 申请人: Serafino Bueti , Kenneth J. Goodnow , Todd E. Leonard , Gregory J. Mann , Peter A. Sandon , Peter A. Twombly , Charles S. Woodruff
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Roberts Mlotkowski Safran & Cole, P.C.
- 代理商 David Cain
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. The invention is also directed to a design structure on which a circuit resides.