发明授权
- 专利标题： Power supply circuit that outputs a voltage stepped down from a power supply voltage
- 专利标题（中）： 输出从电源电压降压的电源的电源电路
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申请号： US12404438申请日： 2009-03-16
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公开(公告)号： US08134349B2公开(公告)日： 2012-03-13
- 发明人: Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
- 申请人： Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- 优先权： JP2008-103713 20080411
- 主分类号： G05F1/613
- IPC分类号： G05F1/613
摘要：
A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage.
公开/授权文献
- US20090256542A1 POWER SUPPLY CIRCUIT 公开/授权日：2009-10-15