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公开(公告)号：US20100124093A1
公开(公告)日：2010-05-20
申请号：US12563924
申请日：2009-09-21
CPC分类号： G11C11/22
摘要： A ferroelectric memory of an embodiment of the present invention includes m platelines arranged in a first interconnect layer (m is a positive integer), n bitlines arranged in a second interconnect layer (n is a positive integer), and m×n memory cells arranged at m×n intersection points of the m platelines and the n bitlines, each of the m×n memory cells including a ferroelectric capacitor and a zener diode connected in series between any one of the m platelines and any one of the n bitlines.
摘要翻译： 本发明实施例的铁电存储器包括布置在第一互连层（m为正整数）中的m条线，布置在第二互连层（n为正整数）中的n条位线，m×n个存储器单元布置 在m个平面阵列和n个位线的m×n个交点处，m×n个存储单元中的每一个包括串联连接在n个位线中的任何一个之间的铁电电容器和齐纳二极管。
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公开(公告)号：US07561459B2
公开(公告)日：2009-07-14
申请号：US11898605
申请日：2007-09-13
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： This disclosure concerns a semiconductor memory device including a ferroelectric capacitor; a cell transistor having a source connected to a first electrode of the ferroelectric capacitor; bit lines; word lines; n plate lines corresponding to n column blocks and connected to a second electrodes of the ferroelectric capacitors in the corresponding column blocks, respectively, the n column blocks being obtained by dividing the cell array into the n column blocks for every set of m columns, where n≧2 and m≧2; a plurality of reset transistors connected between the bit lines and the n plate lines; and m reset lines corresponding to the m columns within the column blocks and connected to gates of n reset transistors of the reset transistors, the n reset transistors being respectively provided in n columns respectively included in the n column blocks.
摘要翻译： 本公开涉及包括铁电电容器的半导体存储器件; 电池晶体管，其源极连接到所述铁电电容器的第一电极; 位线 字线 n列板对应于n列块，分别连接到相应列块中的铁电电容器的第二电极，n列块是通过将每个m列的单元阵列划分成n列块而获得的，其中 n> = 2且m> = 2; 多个复位晶体管，连接在所述位线与所述n条线之间; 和m个复位线，其对应于列块内的m列，并连接到复位晶体管的n个复位晶体管的栅极，n个复位晶体管分别设置在分别包含在n个列块中的n列中。
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3.发明授权公开(公告)号：US07518901B2
公开(公告)日：2009-04-14
申请号：US11877890
申请日：2007-10-24
CPC分类号： G11C11/22
摘要： A first ferroelectric memory cell and a second ferroelectric memory cell each include a ferroelectric capacitor and a transistor and each store one set of information. A word-line is shared by the first and second ferroelectric memory cells. A first plate line is connected to the first ferroelectric memory cell and a second plate line is connected to the second ferroelectric memory cell. A selection transistor has one end connected to the first and second ferroelectric memory cells and the other end connected to a bit-line.
摘要翻译： 第一铁电存储器单元和第二铁电存储单元各自包括铁电电容器和晶体管，并且每个存储一组信息。 字线由第一和第二铁电存储器单元共享。 第一板线连接到第一铁电存储单元，第二板线连接到第二铁电存储单元。 选择晶体管的一端连接到第一和第二铁电存储单元，另一端连接到位线。
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公开(公告)号：US20070047288A1
公开(公告)日：2007-03-01
申请号：US11265188
申请日：2005-11-03
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A reference bit line which supplies a reference potential to a sense amplifier circuit is connected to the sense amplifier circuit. A reference potential generating circuit is connected to the reference bit line. The reference potential generating circuit includes a selection transistor which is connected at one end to the reference bit line, and a paraelectric capacitor connected between the other end of the selection transistor and a dummy plate line. A dummy plate line driver is connected to the dummy plate line. The dummy plate line driver drives the dummy plate line to a first voltage which is higher than an operating voltage of the sense amplifier circuit, when the reference potential generating circuit generates the reference potential.
摘要翻译： 向读出放大器电路提供参考电位的参考位线连接到读出放大器电路。 参考电位产生电路连接到参考位线。 参考电位产生电路包括一端连接到参考位线的选择晶体管和连接在选择晶体管的另一端和虚设板线之间的顺电电容器。 虚拟板线驱动器连接到虚拟板线。 当参考电位产生电路产生参考电位时，虚拟板线驱动器将虚拟板线驱动到高于读出放大器电路的工作电压的第一电压。
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公开(公告)号：US07138674B2
公开(公告)日：2006-11-21
申请号：US10624483
申请日：2003-07-23
IPC分类号： H01L31/62
CPC分类号： G11C11/22 , H01L27/11502 , H01L27/11507
摘要： A semiconductor memory device includes a cell block composed of several series-connected units having a ferroelectric capacitor and a cell transistor parallel-connected to the ferroelectric capacitor and a select transistor connected to an end of the cell block. Mutually separated first impurity diffusion layers are formed on the surface of the semiconductor substrate along a first direction, and have a first area. A second impurity diffusion layer is formed on the surface of the semiconductor substrate separated from the end first impurity diffusion layer, and has a second area. A first gate electrode is provided on the semiconductor substrate between the first impurity diffusion layers along a second direction. A second gate electrode is provided on the semiconductor substrate between the end first impurity diffusion layer and the second impurity diffusion layer along a second direction. A contact electrically connects a bit line and the second impurity diffusion layer.
摘要翻译： 半导体存储器件包括由具有铁电电容器和并联连接到铁电电容器的单元晶体管的多个串联单元组成的单元块和连接到单元块的一端的选择晶体管。 相互分离的第一杂质扩散层沿着第一方向形成在半导体衬底的表面上，并且具有第一区域。 在与第一第一杂质扩散层分离的半导体衬底的表面上形成第二杂质扩散层，并具有第二区域。 第一栅电极沿着第二方向设置在第一杂质扩散层之间的半导体衬底上。 第二栅电极沿着第二方向设置在半导体衬底之间的端部第一杂质扩散层和第二杂质扩散层之间。 触点电连接位线和第二杂质扩散层。
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公开(公告)号：US08274846B2
公开(公告)日：2012-09-25
申请号：US12652612
申请日：2010-01-05
IPC分类号： G11C5/14
摘要： A reference voltage generation circuit includes a first node settable at a reference voltage to be any one of a plurality of voltage levels, a second node set at a pre-charge voltage, first and second switches connected in series between the first and second nodes, a plurality of capacitors, each capacitor comprising a first end connected to a connection node between the first and second switches and a second end settable at an independent voltage level, a switch controller configured to turn off the first switch and turn on the second switch in an initial state, and then to turn off the second switch, and then to turn on the first switch, and a voltage controller configured to individually set a voltage at the second end of each capacitor after the first switch is turned on.
摘要翻译： 参考电压产生电路包括可设置为参考电压的第一节点，其为多个电压电平中的任何一个，在预充电电压下设置的第二节点，串联连接在第一和第二节点之间的第一和第二开关， 多个电容器，每个电容器包括连接到第一和第二开关之间的连接节点的第一端和可设置在独立电压电平的第二端;开关控制器，被配置为关闭第一开关并将第二开关导通 初始状态，然后关闭第二开关，然后打开第一开关，并且电压控制器被配置为在第一开关导通之后单独设置每个电容器的第二端处的电压。
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公开(公告)号：US20110044087A1
公开(公告)日：2011-02-24
申请号：US12684375
申请日：2010-01-08
CPC分类号： G11C11/22
摘要： A memory includes ferroelectric capacitors; sense amplifiers configured to detect the data stored in ferroelectric capacitors; and a plate control circuit configured to receive a plate driving signal driving a plate line, a write signal indicating writing of data from an outside to the sense amplifier, and an operation end signal indicating end of an executable period for reading or writing data between the sense amplifier and the outside, the plate control circuit validating or invalidating the plate driving signal based on the write signal and the operation end signal wherein the plate control circuit validates the plate driving signal in the executable period, and the plate control circuit invalidates the plate driving signal at the end of the executable period when the write signal is never activated in the executable period, and keeps the plate driving signal valid when the write signal is activated in the executable period.
摘要翻译： 存储器包括铁电电容器; 感测放大器，被配置为检测存储在铁电电容器中的数据; 以及板控制电路，被配置为接收驱动板线的板驱动信号，指示从外部向读出放大器写入数据的写入信号，以及指示可执行周期结束的操作结束信号，用于在 读出放大器和外部，板控制电路基于写入信号和操作结束信号来验证或使板驱动信号无效，其中板控制电路在可执行周期中验证板驱动信号，并且板控制电路使板 在可执行期间写入信号从不被激活的可执行期间结束时的驱动信号，并且在可执行期间写入信号被激活时，保持板驱动信号有效。
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公开(公告)号：US20080304309A1
公开(公告)日：2008-12-11
申请号：US12132713
申请日：2008-06-04
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： The sense amp circuit includes a first node given a first, positive constant voltage larger than a fixed potential before reading, a second node given a second, negative constant voltage smaller than the fixed potential before reading, and a third node to be connected to the first and second nodes on reading. A first transistor is connected between the first node and the bit line and operative to turn on when the potential on the bit line becomes smaller than the fixed potential. A second transistor is connected between the second node and the bit line and operative to turn on when the potential on the bit line becomes larger than the fixed potential. A first capacitor is connected between the first node and the fixed potential. A second capacitor is connected between the second node and the fixed potential.
摘要翻译： 感测放大器电路包括：第一节点，其被给予大于读取前的固定电位的第一正恒定电压;给定第二节点，给定小于读取前的固定电位的第二负的恒定电压;以及第三节点 第一和第二节点读取。 第一晶体管连接在第一节点和位线之间，并且当位线上的电位变得小于固定电位时可操作地导通。 第二晶体管连接在第二节点和位线之间，并且当位线上的电位变得大于固定电位时可操作地导通。 第一电容器连接在第一节点和固定电位之间。 第二电容器连接在第二节点和固定电位之间。
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公开(公告)号：US07385836B2
公开(公告)日：2008-06-10
申请号：US11265188
申请日：2005-11-03
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A reference bit line which supplies a reference potential to a sense amplifier circuit is connected to the sense amplifier circuit. A reference potential generating circuit is connected to the reference bit line. The reference potential generating circuit includes a selection transistor which is connected at one end to the reference bit line, and a paraelectric capacitor connected between the other end of the selection transistor and a dummy plate line. A dummy plate line driver is connected to the dummy plate line. The dummy plate line driver drives the dummy plate line to a first voltage which is higher than an operating voltage of the sense amplifier circuit, when the reference potential generating circuit generates the reference potential.
摘要翻译： 向读出放大器电路提供参考电位的参考位线连接到读出放大器电路。 参考电位产生电路连接到参考位线。 参考电位产生电路包括一端连接到参考位线的选择晶体管和连接在选择晶体管的另一端和虚设板线之间的顺电电容器。 虚拟板线驱动器连接到虚拟板线。 当参考电位产生电路产生参考电位时，虚拟板线驱动器将虚拟板线驱动到高于读出放大器电路的工作电压的第一电压。
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公开(公告)号：US20080068874A1
公开(公告)日：2008-03-20
申请号：US11898605
申请日：2007-09-13
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： This disclosure concerns a semiconductor memory device including a ferroelectric capacitor; a cell transistor having a source connected to a first electrode of the ferroelectric capacitor; bit lines; word lines; n plate lines corresponding to n column blocks and connected to a second electrodes of the ferroelectric capacitors in the corresponding column blocks, respectively, the n column blocks being obtained by dividing the cell array into the n column blocks for every set of m columns, where n≧2 and m≧2; a plurality of reset transistors connected between the bit lines and the n plate lines; and m reset lines corresponding to the m columns within the column blocks and connected to gates of n reset transistors of the reset transistors, the n reset transistors being respectively provided in n columns respectively included in the n column blocks.
摘要翻译： 本公开涉及包括铁电电容器的半导体存储器件; 电池晶体管，其源极连接到所述铁电电容器的第一电极; 位线 字线 n列板对应于n列块，分别连接到相应列块中的铁电电容器的第二电极，n列块是通过将每个m列的单元阵列划分成n列块而获得的，其中 n> = 2且m> = 2; 多个复位晶体管，连接在所述位线与所述n条线之间; 和m个复位线，其对应于列块内的m列，并连接到复位晶体管的n个复位晶体管的栅极，n个复位晶体管分别设置在分别包含在n个列块中的n列中。
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