Invention Grant
- Patent Title: Arranging through silicon vias in IC layout
- Patent Title (中): 在IC布局中排列硅通孔
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Application No.: US12555981Application Date: 2009-09-09
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Publication No.: US08136084B2Publication Date: 2012-03-13
- Inventor: Donald R. Dean, Jr. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
- Applicant: Donald R. Dean, Jr. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffman Warnick LLC
- Agent Richard Kotulak
- Main IPC: G06F17/52
- IPC: G06F17/52
Abstract:
A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.
Public/Granted literature
- US20110057319A1 ARRANGING THROUGH SILICON VIAS IN IC LAYOUT Public/Granted day:2011-03-10
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