Invention Grant
US08141013B2 Method and system of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models
有权
将片上寄生耦合电容连接到分布式预布置无源模型中的方法和系统
- Patent Title: Method and system of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models
- Patent Title (中): 将片上寄生耦合电容连接到分布式预布置无源模型中的方法和系统
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Application No.: US12494723Application Date: 2009-06-30
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Publication No.: US08141013B2Publication Date: 2012-03-20
- Inventor: Wayne H. Woods , Cole E. Zemke
- Applicant: Wayne H. Woods , Cole E. Zemke
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb I.P. Law Firm, LLC
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models such as distributed transmission line models and on-chip spiral inductor models includes recognizing a passive device such as a distributed transmission line device and an on-chip spiral inductor device, interpreting data obtained from the recognizing the passive device, breaking the passive device into a plurality of sections, the plurality of sections including a terminal of a model call, extracting parameters of the passive device by Layout Versus Schematic (LVS) and parasitic extraction, connecting the terminal to a pre-layout passive network by selectively low and high resistive paths set by the parameters of the passive device depending on whether crossing lines are present or not present in one of the plurality of sections, connecting the terminal to a distributed passive model, and coupling the crossing lines to the terminal via capacitors produced in an extracted netlist with the passive device having distributed coupling to a plurality of crossing lines.
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