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    Method and system of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models
    1.
    发明授权
    Method and system of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models 有权
    将片上寄生耦合电容连接到分布式预布置无源模型中的方法和系统

    公开(公告)号：US08141013B2

    公开(公告)日：2012-03-20

    申请号：US12494723

    申请日：2009-06-30

    Applicant: Wayne H. Woods ,  Cole E. Zemke

    Inventor： Wayne H. Woods ,  Cole E. Zemke

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: A method of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models such as distributed transmission line models and on-chip spiral inductor models includes recognizing a passive device such as a distributed transmission line device and an on-chip spiral inductor device, interpreting data obtained from the recognizing the passive device, breaking the passive device into a plurality of sections, the plurality of sections including a terminal of a model call, extracting parameters of the passive device by Layout Versus Schematic (LVS) and parasitic extraction, connecting the terminal to a pre-layout passive network by selectively low and high resistive paths set by the parameters of the passive device depending on whether crossing lines are present or not present in one of the plurality of sections, connecting the terminal to a distributed passive model, and coupling the crossing lines to the terminal via capacitors produced in an extracted netlist with the passive device having distributed coupling to a plurality of crossing lines.

    Abstract translation: 将片上寄生耦合电容连接到分布式预布置无源模型（例如分布式传输线模型和片上螺旋电感器模型）中的方法包括识别无源器件，例如分布式传输线器件和片上螺旋电感器器件 解释从识别无源设备获取的数据，将无源设备分解为多个部分，所述多个部分包括模型呼叫的终端，通过布局对比示意图（LVS）和寄生提取来提取被动设备的参数， 通过由无源设备的参数设置的选择性低电平和高阻抗路径将终端连接到预布置的无源网络，这取决于是否存在交叉线是否存在多个部分之一，将终端连接到分布式被动 模型，并通过在提取的网表中产生的电容将交叉线耦合到终端 无源器件具有分布耦合到多个交叉线。

    Methods for distributing a random variable using statistically-correct spatial interpolation
    4.
    发明授权
    Methods for distributing a random variable using statistically-correct spatial interpolation 有权
    使用统计学上正确的空间插值来分配随机变量的方法

    公开(公告)号：US07844418B2

    公开(公告)日：2010-11-30

    申请号：US12030462

    申请日：2008-02-13

    Applicant: Jeffrey G. Hemmett ,  Mukesh Kumar ,  Wayne H. Woods, Jr. ,  Cole E. Zemke

    Inventor： Jeffrey G. Hemmett ,  Mukesh Kumar ,  Wayne H. Woods, Jr. ,  Cole E. Zemke

    IPC: G06F17/18 ,  G21C17/00

    CPC classification number: G06F17/18

    Abstract: Methods for distributing a random variable by spatial interpolation with statistical corrections. The method includes assigning a numerical value of the random variable at each vertex of an array of equilateral triangles formed in a planar coordinate frame and defining a plurality of test points at respective spatial locations in the planar coordinate frame that are bounded by the array of equilateral triangles. A numerical value of the random variable is distributed at each of the test points by spatial interpolation from one or more of the numerical values of the random variable assigned at each vertex of the array of equilateral triangles. The method further includes adjusting the numerical value of the random variable distributed at each of the test points with a respective correction factor.

    Abstract translation: 通过统计校正的空间插值分布随机变量的方法。 该方法包括在平面坐标系中形成的等边三角形阵列的每个顶点处分配随机变量的数值，并且在平面坐标系中的由等边阵列限定的相应空间位置处限定多个测试点 三角形。 随机变量的数值通过从等边三角形阵列的每个顶点处分配的随机变量的一个或多个数值中的空间插值分布在每个测试点。 该方法还包括用相应的校正因子来调整在每个测试点分布的随机变量的数值。

    Method and System of Linking On-Chip Parasitic Coupling Capacitance Into Distributed Pre-Layout Passive Models
    5.
    发明申请
    Method and System of Linking On-Chip Parasitic Coupling Capacitance Into Distributed Pre-Layout Passive Models 有权
    将片上寄生耦合电容连接到分布式预布局被动模型中的方法和系统

    公开(公告)号：US20100333051A1

    公开(公告)日：2010-12-30

    申请号：US12494723

    申请日：2009-06-30

    Applicant: Wayne H. Woods ,  Cole E. Zemke

    Inventor： Wayne H. Woods ,  Cole E. Zemke

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: A method of linking on-chip parasitic coupling capacitance into distributed pre-layout passive models such as distributed transmission line models and on-chip spiral inductor models includes recognizing a passive device such as a distributed transmission line device and an on-chip spiral inductor device, interpreting data obtained from the recognizing the passive device, breaking the passive device into a plurality of sections, the plurality of sections including a terminal of a model call, extracting parameters of the passive device by Layout Versus Schematic (LVS) and parasitic extraction, connecting the terminal to a pre-layout passive network by selectively low and high resistive paths set by the parameters of the passive device depending on whether crossing lines are present or not present in one of the plurality of sections, connecting the terminal to a distributed passive model, and coupling the crossing lines to the terminal via capacitors produced in an extracted netlist with the passive device having distributed coupling to a plurality of crossing lines.

    Abstract translation: 将片上寄生耦合电容连接到分布式预布置无源模型（如分布式传输线模型和片上螺旋电感模型）中的方法包括识别无源器件，如分布式传输线器件和片上螺旋电感器器件 解释从识别无源设备获取的数据，将无源设备分解为多个部分，所述多个部分包括模型呼叫的终端，通过布局对比示意图（LVS）和寄生提取来提取被动设备的参数， 通过由无源设备的参数设置的选择性低电平和高阻抗路径将终端连接到预布置的无源网络，这取决于是否存在交叉线是否存在多个部分之一，将终端连接到分布式被动 模型，并通过在提取的网表中产生的电容将交叉线耦合到终端 无源器件具有分布耦合到多个交叉线。

    METHODS FOR DISTRIBUTING A RANDOM VARIABLE USING STATISTICALLY-CORRECT SPATIAL INTERPOLATION
    6.
    发明申请
    METHODS FOR DISTRIBUTING A RANDOM VARIABLE USING STATISTICALLY-CORRECT SPATIAL INTERPOLATION 有权
    使用统计 - 正确空间插值分配随机变量的方法

    公开(公告)号：US20090204367A1

    公开(公告)日：2009-08-13

    申请号：US12030462

    申请日：2008-02-13

    Applicant: Jeffrey G. Hemmett ,  Mukesh Kumar ,  Wayne H. Woods, JR. ,  Cole E. Zemke

    Inventor： Jeffrey G. Hemmett ,  Mukesh Kumar ,  Wayne H. Woods, JR. ,  Cole E. Zemke

    IPC: G06F17/18

    CPC classification number: G06F17/18

    Abstract: Methods for distributing a random variable by spatial interpolation with statistical corrections. The method includes assigning a numerical value of the random variable at each vertex of an array of equilateral triangles formed in a planar coordinate frame and defining a plurality of test points at respective spatial locations in the planar coordinate frame that are bounded by the array of equilateral triangles. A numerical value of the random variable is distributed at each of the test points by spatial interpolation from one or more of the numerical values of the random variable assigned at each vertex of the array of equilateral triangles. The method further includes adjusting the numerical value of the random variable distributed at each of the test points with a respective correction factor.

    Abstract translation: 通过统计校正的空间插值分布随机变量的方法。 该方法包括在平面坐标系中形成的等边三角形阵列的每个顶点处分配随机变量的数值，并且在平面坐标系中的由等边阵列限定的相应空间位置处限定多个测试点 三角形。 随机变量的数值通过从等边三角形阵列的每个顶点处分配的随机变量的一个或多个数值中的空间插值分布在每个测试点。 该方法还包括用相应的校正因子来调整在每个测试点分布的随机变量的数值。

    Method of determining FET source/drain wire, contact, and diffusion resistances in the presence of multiple contacts
    7.
    发明授权
    Method of determining FET source/drain wire, contact, and diffusion resistances in the presence of multiple contacts 失效
    在存在多个触点的情况下确定FET源/漏极线，接触和扩散电阻的方法

    公开(公告)号：US08479131B2

    公开(公告)日：2013-07-02

    申请号：US13038468

    申请日：2011-03-02

    Applicant: Lewis W. Dewey, III ,  Ning Lu ,  Judith H. McCullen ,  Cole E. Zemke

    Inventor： Lewis W. Dewey, III ,  Ning Lu ,  Judith H. McCullen ,  Cole E. Zemke

    IPC: G06F17/50

    CPC classification number: G06F8/61 ,  H01L29/772

    Abstract: A method calculates a total source/drain resistance for a field effect transistor (FET) device. The method counts the number (N) of contacts in each source/drain region of the FET device, partitions each source/drain region into N contact regions and calculates a set of resistances of elements and connections to the FET device. The measured dimensions of widths, lengths, and distances of layout shapes forming the FET and the connections to the FET are determined and a set of weights based on relative widths of the contact regions are computed. The total source/drain resistance of the FET device is determined by summing products of the set of resistances and the set of weights for each of a plurality of contacts in series, the summing being performed for all of the plurality of contacts in one of a source region and a drain region of the FET. A netlist is formed based on the total source resistance and total drain resistance of the FET device.

    Abstract translation: 一种方法计算场效应晶体管（FET）器件的总源极/漏极电阻。 该方法对FET器件的每个源极/漏极区域中的触点数（N）进行计数，将每个源极/漏极区域划分为N个接触区域，并计算元件的电阻和FET器件的连接的集合。 确定形成FET的布局形状和与FET的连接的宽度，长度和距离的测量尺寸，并且计算基于接触区域的相对宽度的一组权重。 FET器件的总源极/漏极电阻通过将串联的电阻的集合和权重集合的乘积相加来确定，所述电阻的集合对于多个触点中的每一个都是串联的，对于所有多个触点中的一个 源极区域和漏极区域。 基于FET器件的总源极电阻和总漏极电阻形成网表。

    METHOD OF DETERMINING FET SOURCE/DRAIN WIRE, CONTACT, AND DIFFUSION RESISTANCES IN THE PRESENCE OF MULTIPLE CONTACTS
    8.
    发明申请
    METHOD OF DETERMINING FET SOURCE/DRAIN WIRE, CONTACT, AND DIFFUSION RESISTANCES IN THE PRESENCE OF MULTIPLE CONTACTS 失效
    在多个联系人的存在下确定FET源/漏线，接触和扩散电阻的方法

    公开(公告)号：US20120227020A1

    公开(公告)日：2012-09-06

    申请号：US13038468

    申请日：2011-03-02

    Applicant: Lewis W. Dewey, III ,  Ning Lu ,  Judith H. McCullen ,  Cole E. Zemke

    Inventor： Lewis W. Dewey, III ,  Ning Lu ,  Judith H. McCullen ,  Cole E. Zemke

    IPC: G06F9/45

    CPC classification number: G06F8/61 ,  H01L29/772

    Abstract: A method calculates a total source/drain resistance for a field effect transistor (FET) device. The method counts the number (N) of contacts in each source/drain region of the FET device, partitions each source/drain region into N contact regions and calculates a set of resistances of elements and connections to the FET device. The measured dimensions of widths, lengths, and distances of layout shapes forming the FET and the connections to the FET are determined and a set of weights based on relative widths of the contact regions are computed. The total source/drain resistance of the FET device is determined by summing products of the set of resistances and the set of weights for each of a plurality of contacts in series, the summing being performed for all of the plurality of contacts in one of a source region and a drain region of the FET. A netlist is formed based on the total source resistance and total drain resistance of the FET device.

    Abstract translation: 一种方法计算场效应晶体管（FET）器件的总源极/漏极电阻。 该方法对FET器件的每个源极/漏极区域中的触点数（N）进行计数，将每个源极/漏极区域划分为N个接触区域，并计算元件的电阻和FET器件的连接的集合。 确定形成FET的布局形状和与FET的连接的宽度，长度和距离的测量尺寸，并且计算基于接触区域的相对宽度的一组权重。 FET器件的总源极/漏极电阻通过将串联的电阻的集合和权重集合的乘积相加来确定，所述电阻的集合对于多个触点中的每一个都是串联的，对于所有多个触点中的一个 源极区域和漏极区域。 基于FET器件的总源极电阻和总漏极电阻形成网表。

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